MMC2107 - Freescale Semiconductor

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Technical Data — MMC2107
Section 6. M•CORE M210 Central Processor Unit (CPU)
6.1 Contents
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6.2 Introduction
6.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
6.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144
6.4 Microarchitecture Summary . . . . . . . . . . . . . . . . . . . . . . . . . .145
6.5 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
6.6 Data Format Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
6.7 Operand Addressing Capabilities . . . . . . . . . . . . . . . . . . . . . .150
6.8 Instruction Set Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
The M•CORE M210 central processor unit (CPU) architecture is one of
the most compact, full 32-bit core implementations available. The
pipelined reduced instruction set computer (RISC) execution unit uses
16-bit instructions to achieve maximum speed and code efficiency, while
conserving on-chip memory resources. The instruction set is designed
to support high-level language implementation. A non-intrusive resident
debugging system supports product development and in-situ testing.
The M•CORE technology library also encompasses a full complement of
on-chip peripheral modules designed specifically for embedded control
applications.
Total system power consumption is determined by all the system
components, rather than the processor core alone. In particular, memory
power consumption (both on-chip and external) is a dominant factor in
total power consumption of the core plus memory subsystem. With this
in mind, the M•CORE instruction set architecture trades absolute
performance capability for reduced total energy consumption. This is
accomplished while maintaining an acceptably high level of performance
at a given clock frequency.
MMC2107 – Rev. 2.0 Technical Data
MOTOROLA M•CORE M210 Central Processor Unit (CPU) 143
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