MMC2107 - Freescale Semiconductor

Freescale Semiconductor, Inc.
Queued Analog-to-Digital Converter (QADC)
18.8.5.3 QADC Control Register 2
Control register 2 (QACR2) is the mode control register for the operation
of queue 2. Software specifies the queue operating mode of queue 2
and may enable a completion and/or a pause interrupt. Most of the bits
are typically written once when the software initializes the QADC and not
changed afterward.
Stop mode resets the register ($007f)
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Freescale Semiconductor, I
Address: 0x00ca_000e and 0x00ca_000f
Read:
Write:
Bit 15 14 13 12 11 10 9 Bit 8
CIE2
Read: Anytime
PIE2
Write: Anytime except stop mode
0
SSE2
MQ212 MQ211 MQ210 MQ29 MQ28
Reset: 0 0 0 0 0 0 0 0
Read:
Write:
Bit 7 6 5 4 3 2 1 Bit 0
RESUME BQ26 BQ25 BQ24 BQ23 BQ22 BQ21 BQ20
Reset: 0 1 1 1 1 1 1 1
Figure 18-10. QADC Control Register 2 (QACR2)
CIE2 — Queue 2 Completion Software Interrupt Enable Bit
CIE2 enables an interrupt upon completion of queue 2. The interrupt
request is initiated when the conversion is complete for the CCW in
queue 2.
1 = Enable an interrupt after an end-of-conversion for queue 2.
0 = Disable the queue completion interrupt associated with
queue 2.
Technical Data MMC2107 – Rev. 2.0
422 Queued Analog-to-Digital Converter (QADC) MOTOROLA
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