MMC2107 - Freescale Semiconductor

Freescale Semiconductor, Inc.
JTAG Test Access Port and OnCE
Functional Description
This signal is asserted the first time the CPU enters the debug state and
remains asserted until the CPU is released by a write to the OnCE
command register with the GO and EX bits set, and a register specified
as either no register selected or the CPUSCR. This signal remains
asserted even though the CPU may enter and exit the debug state for
each instruction executed under control of the OnCE controller.
21.14.4 OnCE Controller Registers
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Freescale Semiconductor, I
21.14.4.1 OnCE Command Register
This section describes the OnCE controller registers:
• OnCE command register (OCMR)
• OnCE control register (OCR)
• OnCE status register (OSR)
All OnCE registers are addressed by means of the RS field in the OCMR,
as shown in Table 21-4.
The OnCE command register (OCMR) is an 8-bit shift register that
receives its serial data from the TDI pin. This register corresponds to the
JTAG IR and is loaded when the update-IR TAP controller state is
entered. It holds the 8-bit commands shifted in during the shift-IR
controller state to be used as input for the OnCE decoder. The OCMR
contains fields for controlling access to a OnCE resource, as well as
controlling single-step operation, and exit from OnCE mode.
Although the OCMR is updated during the update-IR TAP controller
state, the corresponding resource is accessed in the DR scan sequence
of the TAP controller, and as such, the update-DR state must be
transitioned through in order for an access to occur. In addition, the
update-DR state must also be transitioned through in order for the
single-step and/or exit functionality to be performed, even though the
command appears to have no data resource requirement associated
with it.
MMC2107 – Rev. 2.0
Technical Data
MOTOROLA JTAG Test Access Port and OnCE 561
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