MMC2107 - Freescale Semiconductor

Freescale Semiconductor, Inc.
Electrical Specifications
External Interface Timing Characteristics
Table 22-11. External Interface Timing Characteristics (Continued)
(V DD = 2.7 V to 3.6 V, V SS = 0 V, T A = T L to T H )
No. Characteristic (1), (2) Symbol Min Max Unit
24 Data-in valid to CLKOUT high read t DIVCH 22 — ns
25 CLKOUT high to data-in invalid read t CHDII 0 — ns
26 TA, TEA asserted to CLKOUT high t TACH 0.25 t cyc + 14 — ns
27 CLKOUT high to TA, TEA negated t CHTN 0 — ns
nc...
Freescale Semiconductor, I
1. All AC timing is shown with respect to 20% V DD and 80% V DD levels, unless otherwise noted.
2. Timing is not guaranteed during the clock cycle of mode and/or setup changes (for example, changing pin function between
GPIO and primary function, changing GPIO between input/output functions, changing control registers that affect pin
functions).
3. A[22:0], TSIZ[1:0], CS[3:0] valid to R/W (write), OE, EB asserted (minimum) spec is 0 ns. This parameter is characterized
before qualification rather than 100% tested.
4. Write/show data high-Z to OE asserted (minimum) or from EB negated (write — maximum) spec is 0 ns. This parameter
is characterized before qualification rather than 100% tested.
5. To prevent an unintentional assertion glitch of the EB pins during a synchronous reset (and before the reset overrides
configure the chip in a stable mode), leave the port output data register bits associated with the EB GPO default of 1 and
do not pull the pins down with a current load.
6. SHS high to show data or write data invalid (minimum) spec is 0 ns. This parameter is characterized before qualification
rather than 100% tested.
7. Write/show data high-Z and write/show data invalid is 0 ns for synchronous reset conditions.
CLKOUT
4
Figure 22-3. CLKOUT Timing
5
2
1
3
MMC2107 – Rev. 2.0
Technical Data
MOTOROLA Electrical Specifications 597
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