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MMC2107 - Freescale Semiconductor

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<strong>Freescale</strong> <strong>Semiconductor</strong>, Inc.<br />

Queued Analog-to-Digital Converter (QADC)<br />

Digital Control<br />

Situation S3 (Figure 18-25) shows that when the pause feature is in use,<br />

the trigger overrun error status bit is set the same way, and that queue<br />

execution continues unchanged.<br />

T1<br />

T1<br />

T1<br />

T1<br />

Q1:<br />

C1<br />

C2<br />

T2<br />

T2<br />

C3<br />

C4<br />

T2<br />

TOR1<br />

PF1<br />

Q2:<br />

C1<br />

C2<br />

TOR1<br />

CF1<br />

T2<br />

C3<br />

C4<br />

nc...<br />

<strong>Freescale</strong> <strong>Semiconductor</strong>, I<br />

Q1<br />

Q2<br />

QS<br />

IDLE ACTIVE<br />

0000<br />

TOR2<br />

PAUSE<br />

PF2<br />

ACTIVE<br />

IDLE ACTIVE<br />

PAUSE<br />

ACTIVE IDLE<br />

1000 0100 0110 0101 1001 0001 0010<br />

Figure 18-25. CCW Priority Situation 3<br />

The next two situations consider trigger events that occur for the lower<br />

priority queue 2, while queue 1 is actively being serviced.<br />

Situation S4 (Figure 18-26) shows that a queue 2 trigger event that is<br />

recognized while queue 1 is active is saved, and as soon as queue 1 is<br />

finished, queue 2 servicing begins.<br />

Q1:<br />

T1<br />

C1 C2 C3 C4<br />

Q2:<br />

T2<br />

CF1<br />

C1 C2 C3 C4<br />

CF2<br />

TOR2<br />

IDLE<br />

CF2<br />

0000<br />

Q1<br />

IDLE<br />

ACTIVE<br />

IDLE<br />

Q2<br />

IDLE TRIGGERED<br />

ACTIVE IDLE<br />

QS<br />

0000 1000 1011<br />

0010<br />

Figure 18-26. CCW Priority Situation 4<br />

0000<br />

<strong>MMC2107</strong> – Rev. 2.0<br />

Technical Data<br />

MOTOROLA Queued Analog-to-Digital Converter (QADC) 457<br />

For More Information On This Product,<br />

Go to: www.freescale.com

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