MMC2107 - Freescale Semiconductor

Freescale Semiconductor, Inc.
Queued Analog-to-Digital Converter (QADC)
Digital Control
18.10.4 Disabled Mode
When the disabled mode is selected, the queue is not active. Trigger
events cannot initiate queue execution. When both queue 1 and queue 2
are disabled, wait states are not encountered for IPbus accesses of the
RAM. When both queues are disabled, it is safe to change the QCLK
prescaler values.
18.10.5 Reserved Mode
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Freescale Semiconductor, I
18.10.6 Single-Scan Modes
NOTE:
Reserved mode allows for future mode definitions. When the reserved
mode is selected, the queue is not active. It functions the same as
disabled mode.
When the application software wants to execute a single pass through a
sequence of conversions defined by a queue, a single-scan queue
operating mode is selected. By programming the MQ field in QACR1 or
QACR2, these modes can be selected:
• Software-initiated single-scan mode
• External trigger single-scan mode
• External gated single-scan mode
• Interval timer single-scan mode
Queue 2 cannot be programmed for external gated single-scan mode.
In all single-scan queue operating modes, the software must also enable
the queue to begin execution by writing the single-scan enable bit to a 1
in the queue’s control register. The single-scan enable bits, SSE1 and
SSE2, are provided for queue 1 and queue 2 respectively.
Until the single-scan enable bit is set, any trigger events for that queue
are ignored. The single-scan enable bit may be set to a 1 during the write
cycle, which selects the single-scan queue operating mode. The
single-scan enable bit is set through software, but will always read as
a 0. Once set, writing the single-scan enable bit to 0 has no effect. Only
the QADC can clear the single-scan enable bit. The completion flag,
MMC2107 – Rev. 2.0
Technical Data
MOTOROLA Queued Analog-to-Digital Converter (QADC) 467
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