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MMC2107 - Freescale Semiconductor

MMC2107 - Freescale Semiconductor

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<strong>Freescale</strong> <strong>Semiconductor</strong>, Inc.<br />

JTAG Test Access Port and OnCE<br />

Functional Description<br />

TC — Prefetch Transfer Code<br />

This control field is used to drive the CPU TC2–TC0 outputs on the<br />

first instruction pre-fetch caused by issuing a OnCE command with<br />

the GO bit set and not ignored. It should typically be set to indicate a<br />

supervisor instruction access, for example, 0b110. This field should<br />

be restored to its original value after a debug session is completed,<br />

for example, when a OnCE command is issued with the GO and EX<br />

bits set and not ignored.<br />

nc...<br />

<strong>Freescale</strong> <strong>Semiconductor</strong>, I<br />

21.14.12.4 Writeback Bus Register<br />

21.14.12.5 Processor Status Register<br />

The writeback bus register (WBBR) is a means of passing operand<br />

information between the CPU and the external command controller.<br />

Whenever the external command controller needs to read the contents<br />

of a register or memory location, it forces the device to execute an<br />

instruction that brings that information to WBBR.<br />

For example, to read the content of processor register r0, a MOV r0,r0<br />

instruction is executed, and the result value of the instruction is latched<br />

into the WBBR. The contents of WBBR can then be delivered serially to<br />

the external command controller.<br />

To update a processor resource, this register is initialized with a data<br />

value to be written, and a MOV instruction is executed which uses this<br />

value as a write-back data value. The FFY bit in the CTL register forces<br />

the value of the WBBR to be substituted for the normal source value of<br />

a MOV instruction, thus allowing updates to processor registers to be<br />

performed.<br />

The processor status register (PSR) is a 32-bit latch used to read or write<br />

the M•CORE processor status register. Whenever the external<br />

command controller needs to save or modify the contents of the<br />

M•CORE processor status register, the PSR is used. This register is<br />

affected by the operations performed in debug mode and must be<br />

restored by the external command controller when returning to normal<br />

mode.<br />

<strong>MMC2107</strong> – Rev. 2.0<br />

Technical Data<br />

MOTOROLA JTAG Test Access Port and OnCE 579<br />

For More Information On This Product,<br />

Go to: www.freescale.com

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