MMC2107 - Freescale Semiconductor

Freescale Semiconductor, Inc.
JTAG Test Access Port and OnCE
Functional Description
OnCE resource to be accessed as a DR during the TAP controller
capture-DR, shift-DR and update-DR states.
OnCE COMMAND REGISTER
TDI
TCLK
nc...
ISBKPT
ISTRACE
ISDR
OnCE
DECODER
OnCE TAP
CONTROLLER
TMS
Freescale Semiconductor, I
21.14.3 OnCE Interface Signals
REGISTER
READ
CPU
CONTROL/
STATUS
REGISTER
WRITE
OnCE STATUS
AND CONTROL
REGISTERS
Figure 21-7. OnCE Controller and Serial Interface
The following paragraphs describe the OnCE interface signals to other
internal blocks associated with the OnCE controller. These signals are
not available externally, and descriptions are provided to improve
understanding of OnCE operation.
TDO
21.14.3.1 Internal Debug Request Input (IDR)
The internal debug request input is a hardware signal which is used in
some implementations to force an immediate debug request to the CPU.
If present and enabled, it functions in an identical manner to the control
function provided by the DR control bit in the OCR. This input is
maskable by a control bit in the OCR.
MMC2107 – Rev. 2.0
Technical Data
MOTOROLA JTAG Test Access Port and OnCE 559
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