MMC2107 - Freescale Semiconductor

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Freescale Semiconductor, Inc. M•CORE M210 Central Processor Unit (CPU) 6.7 Operand Addressing Capabilities M•CORE accesses all memory operands through load and store instructions, transferring data between the general-purpose registers and memory. Register-plus-four-bit scaled displacement addressing mode is used for load and store instructions addressing byte, half-word, and word data. nc... Freescale Semiconductor, I 6.8 Instruction Set Overview Load and store multiple instructions allow a subset of the 16 general-purpose registers to be transferred to or from a base address pointed to by register R0 (the default stack pointer by convention). Load and store register quadrant instructions use register indirect addressing to transfer a register quadrant to or from memory. The instruction set is tailored to support high-level languages and is optimized for those instructions most commonly executed. A standard set of arithmetic and logical instructions is provided, as well as instruction support for bit operations, byte extraction, data movement, control flow modification, and a small set of conditionally executed instructions which can be useful in eliminating short conditional branches. Table 6-1 is an alphabetized listing of the M•CORE instruction set. Refer to the M•CORE Reference Manual (Motorola document order number MCORERM/AD) for more details on instruction operation. Mnemonic ABS ADDC ADDI ADDU AND ANDI ANDN ASR ASRC Table 6-1. M•CORE Instruction Set (Sheet 1 of 3) Description Absolute Value Add with C Bit Add Immediate Add Unsigned Logical AND Logical AND Immediate AND NOT Arithmetic Shift Right Arithmetic Shift Right, Update C Bit Technical Data MMC2107 – Rev. 2.0 150 M•CORE M210 Central Processor Unit (CPU) MOTOROLA For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. M•CORE M210 Central Processor Unit (CPU) Instruction Set Overview Table 6-1. M•CORE Instruction Set (Sheet 2 of 3) nc... Freescale Semiconductor, I Mnemonic BCLRI BF BGENI BGENR BKPT BMASKI BR BREV BSETI BSR BT BTSTI CLRF CLRT CMPHS CMPLT CMPLTI CMPNE CMPNEI DECF DECGT DECLT DECNE DECT DIVS DIVU DOZE FF1 INCF INCT IXH IXW JMP JMPI JSR JSRI LD.[BHW] LDM LDQ LOOPT LRW LSL, LSR LSLC, LSRC LSLI, LSRI Bit Clear Immediate Branch on Condition False Bit Generate Immediate Bit Generate Register Breakpoint Bit Mask Immediate Branch Bit Reverse Bit Set Immediate Branch to Subroutine Branch on Condition True Bit Test Immediate Clear Register on Condition False Clear Register on Condition True Compare Higher or Same Compare Less Than Compare Less Than Immediate Compare Not Equal Compare Not Equal Immediate Decrement on Condition False Decrement Register and Set Condition if Result Greater Than Zero Decrement Register and Set Condition if Result Less Than Zero Decrement Register and Set Condition if Result Not Equal to Zero Decrement on Condition True Divide Signed Integer Divide Unsigned Integer Doze Find First One Increment on Condition False Increment on Condition True Index Half-Word Index Word Jump Jump Indirect Jump to Subroutine Jump to Subroutine Indirect Description Load Load Multiple Registers Load Register Quadrant Decrement with C-Bit Update and Branch if Condition True Load Relative Word Logical Shift Left and Right Logical Shift Left and Right, Update C Bit Logical Shift Left and Right by Immediate MMC2107 – Rev. 2.0 Technical Data MOTOROLA M•CORE M210 Central Processor Unit (CPU) 151 For More Information On This Product, Go to: www.freescale.com
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MMC2107 - Freescale Semiconductor

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