MMC2107 - Freescale Semiconductor

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Edge Port Module (EPORT) Freescale Semiconductor, Inc. EPPAR[2n, 2n + 1] STOP MODE EDGE DETECT LOGIC nc... Freescale Semiconductor, I IPBUS EPFR[n] EPPDR[n] SYNCHRONIZER EPIER[n] EPDR[n] EPDDR[n] 12.3 Low-Power Mode Operation 12.3.1 Wait and Doze Modes RISING EDGE OF CLOCK Figure 12-1. EPORT Block Diagram D0 D1 Q INTx PIN This subsection describes the operation of the EPORT module in low-power modes. In wait and doze modes, the EPORT module continues to operate normally and may be configured to exit the low-power modes by generating an interrupt request on either a selected edge or a low level on an external pin. D0 D1 Q TO INTERRUPT CONTROLLER Technical Data MMC2107 – Rev. 2.0 262 Edge Port Module (EPORT) MOTOROLA For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. Edge Port Module (EPORT) Interrupt/General-Purpose I/O Pin Descriptions 12.3.2 Stop Mode In stop mode, there are no clocks available to perform the edge-detect function. Only the level-detect logic is active (if configured) to allow any low level on the external interrupt pin to generate an interrupt (if enabled) to exit stop mode. NOTE: The input pin synchronizer is bypassed for the level-detect logic since no clocks are available. nc... Freescale Semiconductor, I 12.4 Interrupt/General-Purpose I/O Pin Descriptions 12.5 Memory Map and Registers 12.5.1 Memory Map All pins default to general-purpose input pins at reset. The pin value is synchronized to the rising edge of CLKOUT when read from the EPORT pin data register (EPPDR). The values used in the edge/level detect logic are also synchronized to the rising edge of CLKOUT. These pins use Schmitt triggered input buffers which have built in hysteresis designed to decrease the probability of generating false edge-triggered interrupts for slow rising and falling input signals. This subsection describes the memory map and register structure. Refer to Table 12-1 for a description of the EPORT memory map. The EPORT has a base address of 0x00c6_0000. Table 12-1. Edge Port Module Memory Map Address Bits 15–8 Bits 7–0 Access (1) 0x00c6_0000 EPORT pin assignment register (EPPAR) S 0x00c6_0002 EPORT data direction register (EPDDR) EPORT interrupt enable register (EPIER) S 0x00c6_0004 EPORT data register (EPDR) EPORT pin data register (EPPDR) S/U 0x00c6_0006 EPORT flag register (EPFR) Reserved (2) S/U 1. S = CPU supervisor mode access only. S/U = CPU supervisor or user mode access. User mode accesses to supervisor only addresses have no effect and result in a cycle termination transfer error. 2. Writing to reserved address locations has no effect, and reading returns 0s. MMC2107 – Rev. 2.0 Technical Data MOTOROLA Edge Port Module (EPORT) 263 For More Information On This Product, Go to: www.freescale.com
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