MMC2107 - Freescale Semiconductor

Freescale Semiconductor, Inc.
Queued Analog-to-Digital Converter (QADC)
Figure 18-48 shows the timing for conversions in gated mode single
scan with same assumptions in example 1 except:
• No pause bits set in any CCW
• External trigger gated mode single scan for Q1
• Single scan bit is set.
When the gate closes and opens again, the conversions start with the
first CCW in Q1.
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Freescale Semiconductor, I
When the gate closes, the active conversion completes before the
queue goes idle.
When Q1 completes both the CF1 bit sets and the SSE bit clears.
A proposed amended definition for the PF bit in this mode, to reflect the
condition that a gate closing occurred before the queue completed, is
under consideration.
Figure 18-49 shows the timing for conversions in gated mode
continuous scan with the same assumptions as in Figure 18-48.
At the end of Q1,the completion flag CF1 sets and the queue restarts. If
the queue starts a second time and completes, the trigger overrun flag
TOR1 sets.
18.11.4 Analog Supply Filtering and Grounding
Two important factors influencing performance in analog integrated
circuits are supply filtering and grounding. Generally, digital circuits use
bypass capacitors on every V DD /V SS pin pair. This applies to analog
subsystems or submodules also. Equally important as bypassing is the
distribution of power and ground.
Technical Data MMC2107 – Rev. 2.0
490 Queued Analog-to-Digital Converter (QADC) MOTOROLA
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