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MMC2107 - Freescale Semiconductor

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<strong>Freescale</strong> <strong>Semiconductor</strong>, Inc.<br />

Queued Analog-to-Digital Converter (QADC)<br />

18.8.5 Control Registers<br />

This subsection describes the QADC control registers.<br />

18.8.5.1 Control Register 0<br />

Control register 0 (QACR0) establishes the QCLK with prescaler<br />

parameter fields and defines whether external multiplexing is enabled.<br />

They are typically written once when the software initializes the QADC<br />

and not changed afterward.<br />

nc...<br />

<strong>Freescale</strong> <strong>Semiconductor</strong>, I<br />

Address: 0x00ca_000a and 0x00ca_000b<br />

Read:<br />

Write:<br />

Bit 15 14 13 12 11 10 9 Bit 8<br />

MUX<br />

Read: Anytime<br />

0 0<br />

Write: Anytime except stop mode<br />

TRG<br />

0 0 0<br />

Reset: 0 0 0 0 0 0 0 0<br />

Read:<br />

Write:<br />

PSH8<br />

Bit 7 6 5 4 3 2 1 Bit 0<br />

PSH7 PSH6 PSH5 PSH4 PSA PSL2 PSL1 PSL0<br />

Reset: 0 0 1 1 0 1 1 1<br />

= Writes have no effect and the access terminates without a transfer error exception.<br />

Figure 18-8. QADC Control Register 0 (QACR0)<br />

MUX — Externally Multiplexed Mode Bit<br />

The MUX bit allows the software to select the externally multiplexed<br />

mode, which affects the interpretation of the channel numbers and<br />

forces the MA[1:0] pins to be outputs.<br />

1 = Externally multiplexed, 18 possible channels<br />

0 = Internally multiplexed, eight possible channels<br />

Technical Data <strong>MMC2107</strong> – Rev. 2.0<br />

416 Queued Analog-to-Digital Converter (QADC) MOTOROLA<br />

For More Information On This Product,<br />

Go to: www.freescale.com

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