MMC2107 - Freescale Semiconductor

Freescale Semiconductor, Inc.
Chip Select Module
Memory Map and Registers
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Freescale Semiconductor, I
Address: 0x00c2_00006 and 0x00c2_0007
Read:
Write:
Bit 15 14 13 12 11 10 9 Bit 8
SO RO PS WWS WE WS2 WS1 WS0
Reset: 0 0 1 1 1 1 1 1
Bit 7 6 5 4 3 2 1 Bit 0
Read: 0 0 0 0 0 0
Write:
TAEN
Reset: 0 0 0 0 0 0 1 0
CSEN
= Writes have no effect and the access terminates without a transfer error exception.
Figure 20-5. Chip Select Control Register 3 (CSCR3)
SO — Supervisor-Only Bit
The SO bit restricts user mode access to the address range defined
by the corresponding chip select. If the SO bit is 1, only supervisor
mode access is permitted. If the SO bit is 0, both supervisor and user
level accesses are permitted.
When an access is made to a memory space assigned to the chip
select, the chip select logic compares the SO bit with bit 2 of the
internal transfer code, which indicates whether the access is at the
supervisor or user level. If the chip select logic detects a protection
violation, the access is ignored.
1 = Only supervisor mode accesses allowed; user mode accesses
ignored by chip select logic
0 = Supervisor and user mode accesses allowed
RO — Read-Only Bit
The RO bit restricts write accesses to the address range defined by
the corresponding chip select. If the RO bit is 1, only read access is
permitted. If the RO bit is 0, both read and write accesses are
permitted.
When an access is made to a memory space assigned to the chip
select, the chip select logic compares the RO bit with the internal
MMC2107 – Rev. 2.0
Technical Data
MOTOROLA Chip Select Module 527
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