MMC2107 - Freescale Semiconductor

JTAG Test Access Port and OnCE
Freescale Semiconductor, Inc.
21.14.11 Enabling OnCE Memory Breakpoints
When the OnCE memory breakpoint mechanism is enabled with a
breakpoint counter value of zero, the device enters debug mode after
completing the execution of the instruction that caused the memory
breakpoint to occur. In case of breakpoints on instruction fetches, the
breakpoint is acknowledged immediately after the execution of the
fetched instruction. In case of breakpoints on data memory addresses,
the breakpoint is acknowledged after the completion of the memory
access instruction.
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Freescale Semiconductor, I
21.14.12 Pipeline Information and Write-Back Bus Register
A number of on-chip registers store the CPU pipeline status and are
configured in the CPU scan chain register (CPUSCR) for access by the
OnCE controller. The CPUSCR is used to restore the pipeline and
resume normal device activity upon return from debug mode. The
CPUSCR also provides a mechanism for the emulator software to
access processor and memory contents. Figure 21-13 shows the block
diagram of the pipeline information registers contained in the CPUSCR.
31
WBBR
31 0
PSR
31 0
0
TDO
PC
15
0
15
0
TDI
CTL
IR
Figure 21-13. CPU Scan Chain Register (CPUSCR)
Technical Data MMC2107 – Rev. 2.0
576 JTAG Test Access Port and OnCE MOTOROLA
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