MMC2107 - Freescale Semiconductor

Interrupt Controller Module
Freescale Semiconductor, Inc.
ME — Mask Enable Bit
The read/write ME bit enables interrupt masking. Reset clears ME.
1 = Interrupt masking enabled
0 = Interrupt masking disabled
nc...
Freescale Semiconductor, I
MFI — Mask Fast Interrupts Bit
The read/write MFI bit enables masking of fast interrupt requests.
Reset clears MFI.
1 = Fast interrupt requests masked by MASK value. All normal
interrupt requests are masked.
0 = Fast interrupt requests are not masked regardless of the MASK
value. The MASK only applies to normal interrupts. Reset
clears MFI.
MASK[4:0] — Interrupt Mask Field
The read/write MASK[4:0] field determines which interrupt priority
levels are masked. When the ME bit is set, all pending interrupt
requests at priority levels at and below the current MASK value are
masked. To mask all normal interrupts without masking any fast
interrupts, set the MASK value to 31 with the MFI bit cleared. See
Table 7-2. Reset clears MASK[4:0].
Decimal
Table 7-2. MASK Encoding
MASK[4:0]
Binary
Masked Priority
Levels
0 00000 0
1 00001 1–0
2 00010 2–0
3 00011 3–0
•
•
•
•
•
•
31 11111 31–0
•
•
•
Technical Data MMC2107 – Rev. 2.0
158 Interrupt Controller Module MOTOROLA
For More Information On This Product,
Go to: www.freescale.com