MMC2107 - Freescale Semiconductor

Static Random-Access Memory (SRAM)
Freescale Semiconductor, Inc.
8.4 Low-Power Modes
In wait, doze, and stop modes, clocks to the SRAM are disabled. No
recovery time is required when exiting any low-power mode.
8.5 Standby Power Supply Pin (V STBY )
The standby power supply pin (V STBY ) provides standby voltage to the
RAM array if V DD is lost. V STBY is isolated from all other V DD nodes.
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Freescale Semiconductor, I
8.6 Standby Operation
When the chip is powered down, the contents of the SRAM array are
maintained by the standby power supply, V STBY . If the standby voltage
falls below the minimum required voltage, the SRAM contents may be
corrupted. The SRAM automatically switches to standby operation with
no loss of data when the voltage on V DD is below the voltage on V STBY .
In standby mode, the SRAM does not respond to any bus cycles.
Unexpected operation may occur if the central processor unit (CPU)
requests data from the SRAM in standby mode. If standby operation is
not needed, then the V STBY pin should be connected to V DD .
The current on V STBY may exceed its specified maximum value at some
time during the transition time during which V DD is at or below the
voltage switch threshold to a threshold above V SS . If the standby power
supply cannot provide enough current to maintain V STBY above the
required minimum value, then a capacitor must be provided from V STBY
to V SS . The value of the capacitor, C, can be calculated as:
t
C = I × ---
V
where:
I is the difference between the transition current requirement and the
maximum power supply current,
t is the duration of the V DD transition near the voltage switch
threshold, and
V is the difference between the minimum available supply voltage and
the required minimum V STBY voltage.
Technical Data MMC2107 – Rev. 2.0
176 Static Random-Access Memory (SRAM) MOTOROLA
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