MMC2107 - Freescale Semiconductor

Serial Peripheral Interface Module (SPI)
Freescale Semiconductor, Inc.
17.7.2 SPI Control Register 2
Address: 0x00cb_0001
Bit 7 6 5 4 3 2 1 Bit 0
Read: 0 0 0 0 0 0
Write:
SPISDOZ
SPC0
Reset: 0 0 0 0 0 1 0 0
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Freescale Semiconductor, I
Read: Anytime
= Writes have no effect and the access terminates without a transfer error exception.
Figure 17-3. SPI Control Register 2 (SPICR2)
Write: Anytime; writing to unimplemented bits has no effect
SPISDOZ — SPI Stop in Doze Bit
The SPIDOZ bit stops the SPI clocks when the CPU is in doze mode.
Reset clears SPISDOZ.
1 = SPI inactive in doze mode
0 = SPI active in doze mode
SPC0 — Serial Pin Control Bit 0
The SPC0 bit enables the bidirectional pin configurations shown in
Table 17-4. Reset clears SPC0.
Table 17-4. Bidirectional Pin Configurations
Pin Mode SPC0 MSTR MISO Pin (1) MOSI Pin (2) SCK Pin (3) SS Pin (4)
A
0 Slave data output Slave data input SCK input Slave-select input
Normal 0
MODF input (DDRSP3 = 0)
B 1 Master data input Master data output SCK output
or GP output (DDRSP3 = 1)
C
0 Slave data I/O GP (5) I/O SCK input Slave-select input
Bidirectional 1
MODF input (DDRSP3 = 0)
D 1 GP I/O Master data I/O SCK output
or GP output (DDRSP3 = 1)
1. Slave output is enabled if SPIDDR bit 0 = 1, SS = 0, and MSTR = 0 (A, C).
2. Master output is enabled if SPIDDR bit 1 = 1 and MSTR = 1 (B, D).
3. SCK output is enabled if SPIDDR bit 2 = 1 and MSTR = 1 (B, D).
4. SS output is enabled if SPIDDR bit 3 = 1, SPICR1 bit 1 (SSOE) = 1, and MSTR = 1 (B, D).
5. GP = General-purpose
Technical Data MMC2107 – Rev. 2.0
378 Serial Peripheral Interface Module (SPI) MOTOROLA
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