MMC2107 - Freescale Semiconductor

Freescale Semiconductor, Inc.
System Memory Map
Register Map
Address Register Name Bit Number
Bit 7 6 5 4 3 2 1 Bit 0
nc...
Freescale Semiconductor, I
0x00c0_002c
0x00c0_002d
↓
0x00c0_002f
0x00c0_0030
0x00c0_0031
0x00c0_0032
↓
0x00c0_003f
0x00c0_0040
↓
0x00c0_ffff
Port I Clear Output
Data Register (CLRI)
See page 254.
Reserved
Port C/D Pin
Assignment Register
(PCDPAR)
See page 255.
Port E Pin
Assignment Register
(PEPAR)
See page 256.
Reserved
Reserved
Read: 0 0 0 0 0 0 0 0
Write: CLRI7 CLRI6 CLRI5 CLRI4 CLRI3 CLRI2 CLRI1 CLRI0
Reset: 0 0 0 0 0 0 0 0
Read:
Write:
Bit 7 6 5 4 3 2 1 Bit 0
Writes have no effect, reads return 0s, and the access terminates
without a transfer error exception.
Bit 7 6 5 4 3 2 1 Bit 0
PCDPA
0 0 0 0 0 0 0
Reset: See note 0 0 0 0 0 0 0
Read:
Write:
Note: Reset state determined during reset configuration. PCDPA = 1 except in single-chip
mode or when an external boot device is selected with a 16-bit port size in master mode.
Bit 7 6 5 4 3 2 1 Bit 0
PEPA7 PEPA6 PEPA5 PEPA4 PEPA3 PEPA2 PEPA1 PEPA0
Reset: Reset state determined during reset configuration as shown in Table 11-2. PEPAR Reset Values.
Bit 7 6 5 4 3 2 1 Bit 0
Writes have no effect, reads return 0s, and the access terminates
without a transfer error exception.
Bit 7 6 5 4 3 2 1 Bit 0
Ports register space (block of 0x00c0_0000 through 0x00c0_oo3f) is mirrored/repeated.
P = Current pin state U = Unaffected = Writes have no effect and the access terminates without a transfer error exception.
Figure 2-2. Register Summary (Sheet 6 of 34)
MMC2107 – Rev. 2.0
Technical Data
MOTOROLA System Memory Map 59
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