MMC2107 - Freescale Semiconductor

Clock Module
Freescale Semiconductor, Inc.
10.8.6.3 Voltage Control Output (VCO)
The voltage across the loop filter controls the frequency of the VCO
output. The frequency-to-voltage relationship (VCO gain) is positive, and
the output frequency is four times the target system frequency.
10.8.6.4 Multiplication Factor Divider (MFD)
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Freescale Semiconductor, I
10.9 Reset
10.10 Interrupts
When the PLL is not in 1:1 PLL mode, the MFD divides the output of the
VCO and feeds it back to the PFD. The PFD controls the VCO frequency
via the charge pump and loop filter such that the reference and feedback
clocks have the same frequency and phase. Thus, the frequency of the
input to the MFD, which is also the output of the VCO, is the reference
frequency multiplied by the same amount that the MFD divides by. For
example, if the MFD divides the VCO frequency by six, the PLL is
frequency locked when the VCO frequency is six times the reference
frequency. The presence of the MFD in the loop allows the PLL to
perform frequency multiplication, or synthesis.
In 1:1 PLL mode, the MFD is bypassed, and the effective multiplication
factor is one.
The clock module can assert a reset when a loss of clock or loss of lock
occurs as described in 10.8 Functional Description.
Reset initializes the clock module registers to a known startup state as
described in 10.7 Memory Map and Registers.
The clock module does not generate interrupt requests.
Technical Data MMC2107 – Rev. 2.0
246 Clock Module MOTOROLA
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