MMC2107 - Freescale Semiconductor

JTAG Test Access Port and OnCE
Freescale Semiconductor, Inc.
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Freescale Semiconductor, I
21.13.4 Debug Mode Select (TMS). . . . . . . . . . . . . . . . . . . . . . . .556
21.13.5 Test Reset (TRST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .556
21.13.6 Debug Event (DE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .556
21.14 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .556
21.14.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .557
21.14.2 OnCE Controller and Serial Interface. . . . . . . . . . . . . . . .558
21.14.3 OnCE Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . .559
21.14.3.1 Internal Debug Request Input (IDR) . . . . . . . . . . . . . .559
21.14.3.2 CPU Debug Request (DBGRQ). . . . . . . . . . . . . . . . . .560
21.14.3.3 CPU Debug Acknowledge (DBGACK). . . . . . . . . . . . .560
21.14.3.4 CPU Breakpoint Request (BRKRQ). . . . . . . . . . . . . . .560
21.14.3.5 CPU Address, Attributes (ADDR, ATTR) . . . . . . . . . . .560
21.14.3.6 CPU Status (PSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . .560
21.14.3.7 OnCE Debug Output (DEBUG) . . . . . . . . . . . . . . . . . .560
21.14.4 OnCE Controller Registers. . . . . . . . . . . . . . . . . . . . . . . .561
21.14.4.1 OnCE Command Register . . . . . . . . . . . . . . . . . . . . . .561
21.14.4.2 OnCE Control Register . . . . . . . . . . . . . . . . . . . . . . . .564
21.14.4.3 OnCE Status Register . . . . . . . . . . . . . . . . . . . . . . . . .568
21.14.5 OnCE Decoder (ODEC) . . . . . . . . . . . . . . . . . . . . . . . . . .570
21.14.6 Memory Breakpoint Logic . . . . . . . . . . . . . . . . . . . . . . . .570
21.14.6.1 Memory Address Latch (MAL) . . . . . . . . . . . . . . . . . . .571
21.14.6.2 Breakpoint Address Base Registers . . . . . . . . . . . . . .571
21.14.7 Breakpoint Address Mask Registers . . . . . . . . . . . . . . . .571
21.14.7.1 Breakpoint Address Comparators . . . . . . . . . . . . . . . .572
21.14.7.2 Memory Breakpoint Counters . . . . . . . . . . . . . . . . . . .572
21.14.8 OnCE Trace Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .572
21.14.8.1 OnCE Trace Counter . . . . . . . . . . . . . . . . . . . . . . . . . .573
21.14.8.2 Trace Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .574
21.14.9 Methods of Entering Debug Mode . . . . . . . . . . . . . . . . . .574
21.14.9.1 Debug Request During RESET . . . . . . . . . . . . . . . . . .574
21.14.9.2 Debug Request During Normal Activity . . . . . . . . . . . .575
21.14.9.3 Debug Request During Stop, Doze, or Wait Mode . . .575
21.14.9.4 Software Request During Normal Activity . . . . . . . . . .575
21.14.10 Enabling OnCE Trace Mode . . . . . . . . . . . . . . . . . . . . . .575
21.14.11 Enabling OnCE Memory Breakpoints . . . . . . . . . . . . . . .576
21.14.12 Pipeline Information and Write-Back Bus Register . . . . .576
21.14.12.1 Program Counter Register. . . . . . . . . . . . . . . . . . . . . .577
21.14.12.2 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . .577
Technical Data MMC2107 – Rev. 2.0
534 JTAG Test Access Port and OnCE MOTOROLA
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