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MMC2107 - Freescale Semiconductor

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<strong>Freescale</strong> <strong>Semiconductor</strong>, Inc.<br />

Queued Analog-to-Digital Converter (QADC)<br />

In Figure 18-54, R F , R SRC and C F comprise the external filter circuit. C P<br />

is the internal parasitic capacitor. C Samp is the capacitor array used to<br />

sample and hold the input voltage. V I is an internal voltage source used<br />

to provide charge to C samp during sample phase.<br />

The following paragraphs provide a simplified description of the<br />

interaction between the QADC and the user’s external circuitry. This<br />

circuitry is assumed to be a simple RC low-pass filter passing a signal<br />

from a source to the QADC input pin. These simplifying assumptions are<br />

made:<br />

nc...<br />

<strong>Freescale</strong> <strong>Semiconductor</strong>, I<br />

• The external capacitor is perfect (no leakage, no significant<br />

dielectric absorption characteristics, etc.)<br />

• All parasitic capacitance associated with the input pin is included<br />

in the value of the external capacitor.<br />

• Inductance is ignored.<br />

18.11.7.1 Settling Time for the External Circuit<br />

• The "on" resistance of the internal switches is 0 ohms and the "off"<br />

resistance is infinite.<br />

The values for R SRC , R F , and C F in the user's external circuitry<br />

determine the length of time required to charge C F to the source voltage<br />

level (V SRC ). At time t = 0, V src changes in Figure 18-54 while S1 is<br />

open, disconnecting the internal circuitry from the external circuitry.<br />

Assume that the initial voltage across C F is 0. As C F charges, the voltage<br />

across it is determined by the equation, where t is the total charge time:<br />

V CF = V SRC (1 –e –t/(RF + RSRC) CF )<br />

As t approaches infinity, V CF will equal V SRC . (This assumes no internal<br />

leakage.) With 10-bit resolution, 1/2 of a count is equal to 1/2048<br />

full-scale value. Assuming worst case (V SRC = full scale), Table 18-16<br />

shows the required time for C F to charge to within 1/2 of a count of the<br />

actual source voltage during 10-bit conversions. Table 18-16 is based<br />

on the RC network in Figure 18-54.<br />

NOTE:<br />

The following times are completely independent of the A/D converter<br />

architecture (assuming the QADC is not affecting the charging).<br />

Technical Data <strong>MMC2107</strong> – Rev. 2.0<br />

498 Queued Analog-to-Digital Converter (QADC) MOTOROLA<br />

For More Information On This Product,<br />

Go to: www.freescale.com

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