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MMC2107 - Freescale Semiconductor

MMC2107 - Freescale Semiconductor

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<strong>Freescale</strong> <strong>Semiconductor</strong>, Inc.<br />

JTAG Test Access Port and OnCE<br />

Functional Description<br />

21.14.12.1 Program Counter Register<br />

The program counter register (PC) is a 32-bit latch that stores the value<br />

in the CPU program counter when the device enters debug mode. The<br />

CPU PC is affected by operations performed during debug mode and<br />

must be restored by the external command controller when the CPU<br />

returns to normal mode.<br />

21.14.12.2 Instruction Register<br />

nc...<br />

<strong>Freescale</strong> <strong>Semiconductor</strong>, I<br />

21.14.12.3 Control State Register<br />

The instruction register (IR) provides a mechanism for controlling the<br />

debug session. The IR allows the debug control block to execute<br />

selected instructions; the debug control module provides single-step<br />

capability.<br />

When scan-out begins, the IR contains the opcode of the next instruction<br />

to be executed at the time debug mode was entered. This opcode must<br />

be saved in order to resume normal execution at the point debug mode<br />

was entered.<br />

On scan-in, the IR can be filled with an opcode selected by debug control<br />

software in preparation for exiting debug mode. Selecting appropriate<br />

instructions allows a user to examine or change memory locations and<br />

processor registers.<br />

Once the debug session is complete and normal processing is to be<br />

resumed, the IR can be loaded with the value originally scanned out.<br />

The control state register (CTL) is used to set control values when debug<br />

mode is exited. On scan-in, this register is used to control specific<br />

aspects of the CPU. Certain bits reflect internal processor status and<br />

should be restored to their original values.<br />

The CTL register is a 16-bit latch that stores the value of certain internal<br />

CPU state variables before debug mode is entered. This register is<br />

affected by the operations performed during the debug session and<br />

should be restored by the external command controller when returning<br />

to normal mode. In addition to saved internal state variables, the bits are<br />

used by emulation firmware to control the debug process.<br />

<strong>MMC2107</strong> – Rev. 2.0<br />

Technical Data<br />

MOTOROLA JTAG Test Access Port and OnCE 577<br />

For More Information On This Product,<br />

Go to: www.freescale.com

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