MMC2107 - Freescale Semiconductor

Freescale Semiconductor, Inc.
Queued Analog-to-Digital Converter (QADC)
Register Descriptions
18.8.6 Status Registers
This subsection describes the QADC status registers.
18.8.6.1 QADC Status Register 0
The QADC status register 0 (QASR0) contains information about the
state of each queue and the current A/D conversion.
Stop mode resets the register ($0000)
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Address: 0x00ca_0010 and 0x00ca_0011
Read:
Write:
Bit 15 14 13 12 11 10 9 Bit 8
CF1 PF1 CF2 PF2 TOR1 TOR2
Reset: 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 Bit 0
Read: QS7 QS6 CWP5 CWP4 CWP3 CWP2 CWP1 CWP0
Write:
Reset: 0 0 0 0 0 0 0 0
Read: Anytime
Write:
For flag bits (CF1, PF1, CF2, PF2, TOR1, TOR2): Writing a 1 has no
effect, write a 0 to clear.
For QA[9:6] and CWP: Write has no effect.
Never in stop mode
QS9
QS8
= Writes have no effect and the access terminates without a transfer error exception.
Figure 18-11. QADC Status Register 0 (QASR0)
CF1 — Queue 1 Completion Flag
CF1 indicates that a queue 1 scan has been completed. The scan
completion flag is set by the QADC when the input channel sample
requested by the last CCW in queue 1 is converted, and the result is
stored in the result table.
MMC2107 – Rev. 2.0
Technical Data
MOTOROLA Queued Analog-to-Digital Converter (QADC) 427
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