MMC2107 - Freescale Semiconductor

JTAG Test Access Port and OnCE
Freescale Semiconductor, Inc.
Table 21-1. JTAG Instructions
Instruction IR3–IR0 Instruction Summary
EXTEST 0000
Selects the boundary scan register while
applying fixed values to output pins and
asserting functional reset
IDCODE 0001 Selects IDCODE register for shift
SAMPLE/PRELOAD 0010
Selects the boundary scan register for
shifting, sampling, and preloading without
disturbing functional operation
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Freescale Semiconductor, I
21.5.2 IDCODE Instruction
ENABLE_MCU_ONCE 0011
HIGHZ 1001
CLAMP 1100
BYPASS 1111
Reserved
0100
0110
Reserved 0101
Reserved
0111–1000
1101–1110
1010–1011
Instruction to enable the M•CORE TAP
controller
Selects the bypass register while
three-stating all output pins and asserting
functional reset
Selects bypass while applying fixed values to
output pins and asserting functional reset
Selects the bypass register for data
operations
Instruction for chip manufacturing purposes
only
Instruction for chip manufacturing purposes
only (1)
Decoded to select bypass register (2)
1. To exit this instruction, the TRST pin must be asserted or power-on reset.
2. Motorola reserves the right to change the decoding of the unused opcodes in the future.
The IDCODE instruction selects the 32-bit IDCODE register for
connection as a shift path between the TDI pin and the TDO pin. This
instruction allows interrogation of the MMC2107 to determine its version
number and other part identification data. The IDCODE register has
been implemented in accordance with the IEEE 1149.1 standard so that
the least significant bit of the shift register stage is set to logic 1 on the
rising edge of TCLK following entry into the capture-DR state. Therefore,
the first bit to be shifted out after selecting the IDCODE register is always
Technical Data MMC2107 – Rev. 2.0
542 JTAG Test Access Port and OnCE MOTOROLA
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