MMC2107 - Freescale Semiconductor

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JTAG Test Access Port and OnCE Freescale Semiconductor, Inc. Freescale Semiconductor, I nc... DETAILED VIEW OF OnCE DATA REGISTERS BLOCK FOUND IN FIGURE 21-1 RS4–RS0 FROM ONCE CMD (INSTRUCTION) REGISTER, OCMR TDI IN Figure 21-1 (TEST DATA IN) OCMR, RS[4:0] = MUX 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0x1f TRACE COUNTER MSB 15 0 LSB MEMORY BKPT COUNTER (SHIFT) REGISTER, OTC (SHIFT) REGISTER, MBCB B MSB MSB MSB MSB 15 31 31 127 CTL 0 LSB BKPT ADDRESS BASE REGISTER A (SHIFT) REGISTER, BABA 0 LSB BKPT ADDRESS MASK REGISTER A (SHIFT) REGISTER, BAMA 0 LSB CPU SCAN CHAIN REGISTER (SHIFT) REGISTER, CPUSCR IR PC PSR WBBR 112 111 96 95 64 63 32 31 0 LSB OnCE CONTROL REGISTER (SHIFT) REGISTER, OCR SQC DR IDRE TME FRZC RCB BCB RCA BCA MSB 31 17 16 15 14 13 12 11 10 6 5 4 0 LSB BYPASS REGISTER PASS- THROUGH, BYPASS 1 BIT MEMORY BKPT COUNTER A (SHIFT) REGISTER, MBCA MSB 15 PROGRAM COUNTER FIFO AND INCREMENT COUNTER (SHIFT) REGISTER, PC FIFO MSB 31 BKPT ADDRESS BASE REGISTER B (SHIFT) REGISTER, BABB MSB 31 BKPT ADDRESS MASK REGISTER B (SHIFT) REGISTER, BAMB MSB 31 BYPASS REGISTER PASS- OnCE STATUS THROUGH (SHIFT) REGISTER, BYPASS 1 BIT (SHIFT) REGISTER, OSR MSB 15 0 LSB 0 LSB 0 LSB 0 LSB 0 LSB TDO (TEST DATA OUT) Figure 21-5. Low-Level (OnCE) Tap Module Data Registers (DRs) Technical Data MMC2107 – Rev. 2.0 554 JTAG Test Access Port and OnCE MOTOROLA For More Information On This Product, Go to: www.freescale.com
Freescale Semiconductor, Inc. JTAG Test Access Port and OnCE Signal Descriptions 21.13 Signal Descriptions nc... Freescale Semiconductor, I 21.13.1 Debug Serial Input (TDI) 21.13.2 Debug Serial Clock (TCLK) 21.13.3 Debug Serial Output (TDO) The OnCE pin interface is used to transfer OnCE instructions and data to the OnCE control block. Depending on the particular resource being accessed, the CPU may need to be placed in debug mode. For resources outside of the CPU block and contained in the OnCE block, the processor is not disturbed and may continue execution. If a processor resource is required, the OnCE controller may assert a debug request (DBGRQ) to the CPU. This causes the CPU to finish the instruction being executed, save the instruction pipeline information, enter debug mode, and wait for further commands. Asserting DBGRQ causes the device to exit stop, doze, or wait mode. Data and commands are provided to the OnCE controller through the TDI pin. Data is latched on the rising edge of the TCLK serial clock. Data is shifted into the OnCE serial port least significant bit (LSB) first. The TCLK pin supplies the serial clock to the OnCE control block. The serial clock provides pulses required to shift data and commands into and out of the OnCE serial port. (Data is clocked into the OnCE on the rising edge and is clocked out of the OnCE serial port on the falling edge.) The debug serial clock frequency must be no greater than 50 percent of the processor clock frequency. Serial data is read from the OnCE block through the TDO pin. Data is always shifted out the OnCE serial port LSB first. Data is clocked out of the OnCE serial port on the falling edge of TCLK. TDO is three-stateable and is actively driven in the shift-IR and shift-DR controller states. TDO changes on the falling edge of TCLK. MMC2107 – Rev. 2.0 Technical Data MOTOROLA JTAG Test Access Port and OnCE 555 For More Information On This Product, Go to: www.freescale.com
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MMC2107 - Freescale Semiconductor

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