MMC2107 - Freescale Semiconductor

Freescale Semiconductor, Inc.
Queued Analog-to-Digital Converter (QADC)
Digital Control
ZERO
DETECT
SYSTEM CLOCK (f sys )
[5]
5-BIT
DOWN COUNTER
LOAD PSH
HIGH-TIME
CYCLES (PSH) [5]
[3]
CLOCK
GENERATE
QCLK
f sys /2 to f sys /40
nc...
LOW-TIME
CYCLES (PSL) [3]
ONE’S COMPLEMENT
COMPARE
SET QCLK
Freescale Semiconductor, I
SAR CONTROL
INPUT SAMPLE TIME
FROM CCW [2] ATD CONVERTER
SAR [10]
STATE MACHINE
QUEUE1 AND QUEUE2 TIMER
MODE RATE SELECTION [8]
BINARY COUNTER
27 28 29 210 211 212 213 214 215 216 217
PERIODIC TIMER/INTERVAL TIMER
SELECT
Figure 18-42. QADC Clock Subsystem Functions
PERIODIC/INTERVAL TRIGGER
EVENT FOR Q1 AND Q2 [2]
To accommodate wide variations of the main MCU clock frequency
(IPbus system clock – f sys ), QCLK is generated by a programmable
prescaler which divides the MCU system clock. To allow the A/D
conversion time to be maximized across the spectrum of system clock
frequencies, the QADC prescaler permits the frequency of QCLK to be
software selectable. It also allows the duty cycle of the QCLK waveform
to be programmable.
The software establishes the basic high phase of the QCLK waveform
with the PSH (prescaler clock high time) field in QACR0 and selects the
basic low phase of QCLK with the PSL (prescaler clock low time) field.
The combination of the PSH and PSL parameters establishes the
frequency of the QCLK.
MMC2107 – Rev. 2.0
Technical Data
MOTOROLA Queued Analog-to-Digital Converter (QADC) 477
For More Information On This Product,
Go to: www.freescale.com