MMC2107 - Freescale Semiconductor

Freescale Semiconductor, Inc.
Serial Peripheral Interface Module (SPI)
Reset
17.9 Reset
Reset initializes the SPI registers to a known startup state as described
in 17.7 Memory Map and Registers. A transmission from a slave after
reset and before writing to the SPIDR register is either indeterminate or
the byte last received from the master before the reset. Reading the
SPIDR after reset returns 0s.
17.10 Interrupts
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Mode fault
Transmission complete
17.10.1 SPI Interrupt Flag (SPIF)
17.10.2 Mode Fault (MODF) Flag
Table 17-8. SPI Interrupt Request Sources
Interrupt Request Flag Enable Bit
MODF
SPIF
SPIE
SPIF is set after the eighth SCK cycle in a transmission when received
data transfers from the shift register to SPIDR. If the SPIE bit is also set,
SPIF generates an interrupt request. Once SPIF is set, no new data can
be transferred into SPIDR until SPIF is cleared. Clear SPIF by reading
SPISR with SPIF set and then accessing SPIDR. Reset clears SPIF.
MODF is set when the SS pin of a master SPI is driven low and the SS
pin is configured as a mode-fault input. If the SPIE bit is also set, MODF
generates an interrupt request. A mode fault clears the SPE, MSTR, and
DDRSP[2:0] bits. Clear MODF by reading SPISR with MODF set and
then writing to SPICR1. Reset clears MODF.
MMC2107 – Rev. 2.0
Technical Data
MOTOROLA Serial Peripheral Interface Module (SPI) 397
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