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MMC2107 - Freescale Semiconductor

MMC2107 - Freescale Semiconductor

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<strong>Freescale</strong> <strong>Semiconductor</strong>, Inc.<br />

JTAG Test Access Port and OnCE<br />

Instruction Shift Register<br />

a logic 1. The remaining 31 bits are also set to fixed values on the rising<br />

edge of TCLK following entry into the capture-DR state.<br />

IDCODE is the default instruction placed into the instruction register<br />

when the top-level TAP resets. Thus, after a TAP reset, the IDCODE<br />

(data) register will be selected automatically.<br />

21.5.3 SAMPLE/PRELOAD Instruction<br />

The SAMPLE/PRELOAD instruction provides two separate functions.<br />

nc...<br />

<strong>Freescale</strong> <strong>Semiconductor</strong>, I<br />

NOTE:<br />

First, it obtains a sample of the system data and control signals present<br />

at the <strong>MMC2107</strong> input pins and just prior to the boundary scan cell at the<br />

output pins. This sampling occurs on the rising edge of TCLK in the<br />

capture-DR state when an instruction encoding of hex 2 is resident in the<br />

instruction register. The user can observe this sampled data by shifting<br />

it through the boundary scan register to the output TDO by using the<br />

shift-DR state. Both the data capture and the shift operation are<br />

transparent to system operation.<br />

The user is responsible for providing some form of external<br />

synchronization to achieve meaningful results because there is no<br />

internal synchronization between TCLK and the system clock.<br />

The second function of the SAMPLE/PRELOAD instruction is to initialize<br />

the boundary scan register update cells before selecting EXTEST or<br />

CLAMP. This is achieved by ignoring the data being shifted out of the<br />

TDO pin while shifting in initialization data. The update-DR state in<br />

conjunction with the falling edge of TCLK can then transfer this data to<br />

the update cells. This data will be applied to the external output pins<br />

when EXTEST or CLAMP instruction is applied.<br />

21.5.4 ENABLE_MCU_ONCE Instruction<br />

The ENABLE_MCU_ONCE is a public instruction to enable the<br />

M•CORE OnCE TAP controller. When the OnCE TAP controller is<br />

enabled, the top-level TAP controller connects the internal OnCE TDO<br />

to the pin TDO and remains in the run-test/idle state. It will remain in this<br />

state until TRST is asserted. While the OnCE TAP controller is enabled,<br />

the top-level JTAG remains transparent.<br />

<strong>MMC2107</strong> – Rev. 2.0<br />

Technical Data<br />

MOTOROLA JTAG Test Access Port and OnCE 543<br />

For More Information On This Product,<br />

Go to: www.freescale.com

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