MMC2107 - Freescale Semiconductor

Freescale Semiconductor, Inc.
Queued Analog-to-Digital Converter (QADC)
Digital Control
18.10.1.1 Queue Priority
Queue 1 has priority over queue 2 execution. These cases show the
conditions under which queue 1 asserts its priority:
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• When a queue is not active, a trigger event for queue 1 or queue
2 causes the corresponding queue execution to begin.
• When queue 1 is active and a trigger event occurs for queue 2,
queue 2 cannot begin execution until queue 1 reaches completion
or the paused state. The status register records the trigger event
by reporting the queue 2 status as trigger pending. Additional
trigger events for queue 2, which occur before execution can
begin, are captured as trigger overruns.
• When queue 2 is active and a trigger event occurs for queue 1, the
current queue 2 conversion is aborted. The status register reports
the queue 2 status as suspended. Any trigger events occurring for
queue 2 while queue 2 is suspended are captured as trigger
overruns. Once queue 1 reaches the completion or the paused
state, queue 2 begins executing again. The programming of the
RESUME bit in QACR2 determines which CCW is executed in
queue 2.
• When simultaneous trigger events occur for queue 1 and queue 2,
queue 1 begins execution and the queue 2 status is changed to
trigger pending.
• Subqueues that are paused
The pause feature can be used to divide queue 1 and/or queue 2 into
multiple subqueues. A subqueue is defined by setting the pause bit in
the last CCW of the subqueue.
Figure 18-22 shows the CCW format and an example of using pause to
create subqueues. Queue 1 is shown with four CCWs in each subqueue
and queue 2 has two CCWs in each subqueue.
MMC2107 – Rev. 2.0
Technical Data
MOTOROLA Queued Analog-to-Digital Converter (QADC) 451
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