MMC2107 - Freescale Semiconductor

JTAG Test Access Port and OnCE
Freescale Semiconductor, Inc.
21.4 Top-Level TAP Controller
The top-level TAP controller is responsible for interpreting the sequence
of logical values on the TMS signal. It is a synchronous state machine
that controls the operation of the JTAG logic. The machine’s states are
shown in Figure 21-2. The value shown adjacent to each arc represents
the value of the TMS signal sampled on the rising edge of the TCLK
signal.
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Freescale Semiconductor, I
The top-level TAP controller can be asynchronously reset to the testlogic-reset
state by asserting TRST, test reset. As Figure 21-2 shows,
holding TMS high (to logic 1) while clocking TCLK through at least five
rising edges will also cause the state machine to enter its test-logic-reset
state.
1
0
TEST-LOGIC-
RESET
0
RUN-TEST/IDLE
1
1
0
SELECT-DR_SCAN
0
CAPTURE-DR
0
SHIFT-DR
1
EXIT1-DR
0
PAUSE-DR
1
EXIT2-DR
0
0
1
1
1
0
SELECT-IR_SCAN
0
CAPTURE-IR
0
SHIFT-IR
1
EXIT1-IR
0
PAUSE-IR
1
EXIT2-IR
0
0
1
1
1
1
1
UPDATE-DR
UPDATE-IR
1
0 0
Figure 21-2. Top-Level TAP Controller State Machine
Technical Data MMC2107 – Rev. 2.0
540 JTAG Test Access Port and OnCE MOTOROLA
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