MMC2107 - Freescale Semiconductor

Freescale Semiconductor, Inc.
Interrupt Controller Module
Memory Map and Registers
7.7.2.5 Normal Interrupt Enable Register
The read/write, 32-bit normal interrupt enable register (NIER)
individually enables any current pending interrupts which are assigned
to each priority level as a normal interrupt source. Enabling an interrupt
source which has an asserted request causes that request to become
pending, and a request to the M•CORE processor is asserted if not
already outstanding.
Address: 0x00c5_0010 through 0x00c5_0013
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Bit 31 30 29 28 27 26 25 Bit 24
Read:
NIE31 NIE30 NIE29 NIE28 NIE27 NIE26 NIE25 NIE24
Write:
Reset: 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 Bit 16
Read:
NIE23 NIE22 NIE21 NIE20 NIE19 NIE18 NIE17 NIE16
Write:
Reset: 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 Bit 8
Read:
NIE15 NIE14 NIE13 NIE12 NIE11 NIE10 NIE9 NIE8
Write:
Reset: 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 Bit 0
Read:
NIE7 NIE6 NIE5 NIE4 NIE3 NIE2 NIE1 NIE0
Write:
Reset: 0 0 0 0 0 0 0 0
Figure 7-7. Normal Interrupt Enable Register (NIER)
NIE[31:0] — Normal Interrupt Enable Field
The read/write NIE[31:0] field enables interrupt requests from sources
at the corresponding priority level as normal interrupt requests. Reset
clears NIE[31:0].
1 = Normal interrupt request enabled
0 = Normal interrupt request disabled
MMC2107 – Rev. 2.0
Technical Data
MOTOROLA Interrupt Controller Module 163
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