MMC2107 - Freescale Semiconductor

Freescale Semiconductor, Inc.
JTAG Test Access Port and OnCE
Functional Description
vector and the first instruction of the reset exception handler but does not
execute an instruction before entering debug mode.
21.14.9.2 Debug Request During Normal Activity
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Freescale Semiconductor, I
Setting the DR bit in the OCR during normal device activity causes the
device to finish the execution of the current instruction and then enter
debug mode. Note that in this case the device completes the execution
of the current instruction and stops after the newly fetched instruction
enters the CPU instruction latch. This process is the same for any newly
fetched instruction, including instructions fetched by interrupt processing
or those that will be aborted by interrupt processing.
21.14.9.3 Debug Request During Stop, Doze, or Wait Mode
Setting the DR bit in the OCR when the device is in stop, doze, or wait
mode (for instance, after execution of a STOP, DOZE, or WAIT
instruction) causes the device to exit the low-power state and enter the
debug mode. Note that in this case, the device completes the execution
of the STOP, DOZE, or WAIT instruction and halts after the next
instruction enters the instruction latch.
21.14.9.4 Software Request During Normal Activity
21.14.10 Enabling OnCE Trace Mode
Executing the BKPT instruction when the FDB (force debug enable
mode) control bit in the control state register is set causes the CPU to
enter debug mode after the instruction following the BKPT instruction
has entered the instruction latch.
When the OnCE trace mode mechanism is enabled and the trace count
is greater than zero, the trace counter is decremented for each
instruction executed. Completing execution of an instruction when the
trace counter is zero causes the CPU to enter debug mode.
NOTE:
Only instructions actually executed cause the trace counter to
decrement. An aborted instruction does not decrement the trace counter
and does not invoke debug mode.
MMC2107 – Rev. 2.0
Technical Data
MOTOROLA JTAG Test Access Port and OnCE 575
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