MMC2107 - Freescale Semiconductor

Freescale Semiconductor, Inc.
Timer Modules (TIM1 and TIM2)
Modes of Operation
15.5 Modes of Operation
This subsection describes the supervisor and user modes, the five
low-power options, and test mode.
15.5.1 Supervisor and User Modes
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15.5.2 Run Mode
15.5.3 Stop Mode
15.5.4 Wait, Doze, and Debug Modes
The SO bit in the chip-select control register determines whether the
processor is operating in user mode or supervisor mode. Accessing
supervisor address locations while not in supervisor mode causes the
timer to assert a transfer error.
Clearing the TIMEN bit in the timer system control register 1 (TIMSCR1)
or the PAE bit in the pulse accumulator control register (TIMPACTL)
reduces power consumption in run mode. Timer registers are still
accessible, but all timer functions are disabled.
If the central processor unit (CPU) enters stop mode, timer operation
stops. Upon exiting stop mode, the timer resumes operation unless stop
mode was exited by reset.
The timer is unaffected by these low-power modes.
15.5.5 Test Mode
A high signal on the TEST pin puts the processor in test mode or special
mode. The timer behaves as in user mode, except that timer test
registers are accessible.
MMC2107 – Rev. 2.0
Technical Data
MOTOROLA Timer Modules (TIM1 and TIM2) 297
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