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MMC2107 - Freescale Semiconductor

MMC2107 - Freescale Semiconductor

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<strong>Freescale</strong> <strong>Semiconductor</strong>, Inc.<br />

Queued Analog-to-Digital Converter (QADC)<br />

Digital Control<br />

an end-of-queue. However it is useful to take advantage of a smaller<br />

queue in the manner described in the next paragraph.<br />

In the event that the queue completes before the gate closes, a<br />

completion flag will be set and the queue will roll over to the beginning<br />

and continue conversions until the gate closes. If the gate remains open<br />

and the completion flag is not cleared, when the queue completes a<br />

second time the trigger overrun flag will be set and the queue will<br />

roll-over again. The queue will continue to execute until the gate closes<br />

or the mode is disabled.<br />

nc...<br />

<strong>Freescale</strong> <strong>Semiconductor</strong>, I<br />

If the gate closes before queue 1 completes execution, the current CCW<br />

completes execution of queue 1 stops and QADC sets the PF1 bit to<br />

indicate an incomplete queue. Software can read the CWPQ1 to<br />

determine the last valid conversion in the queue. In this mode, if the gate<br />

opens again, execution of queue 1 begins again. The start of queue 1 is<br />

always the first CCW in the CCW table. Since the condition of the gate<br />

is only sampled after each conversion during queue execution, closing<br />

the gate for a period less than a conversion time interval does not<br />

guarantee the closure will be captured.<br />

18.10.7.4 Periodic Timer Continuous-Scan Mode<br />

The QADC includes a dedicated periodic timer for initiating a scan<br />

sequence on queue 1 and/or queue 2. Software selects a programmable<br />

timer interval ranging from 128 to 128K times the QCLK period in binary<br />

multiples. The QCLK period is prescaled down from the IPbus MCU<br />

clock.<br />

When a periodic timer continuous-scan mode is selected for queue 1<br />

and/or queue 2, the timer begins counting. After the programmed<br />

interval elapses, the timer generated trigger event starts the appropriate<br />

queue. Meanwhile, the QADC automatically performs the conversions in<br />

the queue until an end-of-queue condition or a pause is encountered.<br />

When a pause occurs, the QADC waits for the periodic interval to expire<br />

again, then continues with the queue. Once end-of-queue has been<br />

detected, the next trigger event causes queue execution to begin again<br />

with the first CCW in the queue.<br />

The periodic timer generates a trigger event whenever the time interval<br />

elapses. The trigger event may cause the queue execution to continue<br />

following a pause or queue completion, or may be considered a trigger<br />

<strong>MMC2107</strong> – Rev. 2.0<br />

Technical Data<br />

MOTOROLA Queued Analog-to-Digital Converter (QADC) 475<br />

For More Information On This Product,<br />

Go to: www.freescale.com

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