MMC2107 - Freescale Semiconductor

Freescale Semiconductor, Inc.
Serial Communications Interface Modules (SCI1 and SCI2)
FE — Framing Error Flag
The FE flag is set when a logic 0 is accepted as the stop bit. FE is set
during the same cycle as the RDRF flag but does not get set in the
case of an overrun. FE inhibits further data reception until it is cleared.
Clear FE by reading SCISR1 and then reading SCIDRL. Reset clears
FE.
1 = Framing error
0 = No framing error
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Freescale Semiconductor, I
16.7.5 SCI Status Register 2
PF — Parity Error Flag
The PF flag is set when PE = 1 and the parity of the received data
does not match its parity bit. Clear PF by reading SCISR1 and then
reading SCIDRL. Reset clears PF.
1 = Parity error
0 = No parity error
Address: SCI1 — 0x00cc_0005
SCI2 — 0x00cd_0005
Read: Anytime
Bit 7 6 5 4 3 2 1 Bit 0
Read: 0 0 0 0 0 0 0 RAF
Write:
Reset: 0 0 0 0 0 0 0 0
= Writes have no effect and the access terminates without a transfer error exception.
Figure 16-7. SCI Status Register 2 (SCISR2)
Write: Has no meaning or effect
RAF — Receiver Active Flag
The RAF flag is set when the receiver detects a logic 0 during the RT1
time period of the start bit search. When the receiver detects an idle
character, it clears RAF. Reset clears RAF.
1 = Reception in progress
0 = No reception in progress
Technical Data MMC2107 – Rev. 2.0
344 Serial Communications Interface Modules (SCI1 and SCI2) MOTOROLA
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