MMC2107 - Freescale Semiconductor

Freescale Semiconductor, Inc.
JTAG Test Access Port and OnCE
Functional Description
Table 21-5. Sequential Control Field Settings
SQC1
and SQC0
00
Meaning
Disable sequential control operation. Memory breakpoints and trace
operation are unaffected by this field.
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Freescale Semiconductor, I
01
10
11
Suspend normal trace counter operation until a breakpoint condition
occurs for memory breakpoint B. In this mode, memory breakpoint B
occurrences no longer cause breakpoint requests to be generated.
Instead, trace counter comparisons are suspended until the first
memory breakpoint B occurrence. After the first memory breakpoint
B occurrence, trace counter control is released to perform normally,
assuming TME is set. This allows a sequence of breakpoint
conditions to be specified prior to trace counting.
Qualify memory breakpoint B matches with a breakpoint occurrence
for memory breakpoint A. In this mode, memory breakpoint A
occurrences no longer cause breakpoint requests to be generated.
Instead, memory breakpoint B comparisons are suspended until the
first memory breakpoint A occurrence. After the first memory
breakpoint A occurrence, memory breakpoint B is enabled to
perform normally. This allows a sequence of breakpoint conditions
to be specified.
Combine the 01 and 10 qualifications. In this mode, no breakpoint
requests are generated, and trace count operation is enabled once
a memory breakpoint B occurrence follows a memory breakpoint A
occurrence if TME is set.
DR — Debug Request Bit
DR requests the CPU to enter debug mode unconditionally. The PM
bits in the OnCE status register indicate that the CPU is in debug
mode. Once the CPU enters debug mode, it returns there even with
a write to the OCMR with GO and EX set until the DR bit is cleared.
Test logic reset clears the DR bit.
IDRE — Internal Debug Request Enable Bit
The internal debug request (IDR) input to the OnCE control logic may
not be used in all implementations. In some implementations, the IDR
control input may be connected and used as an additional hardware
debug request. Test logic reset clears the IDRE bit.
1 = IDR input enabled
0 = IDR input disabled
MMC2107 – Rev. 2.0
Technical Data
MOTOROLA JTAG Test Access Port and OnCE 565
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