MMC2107 - Freescale Semiconductor

Freescale Semiconductor, Inc.
Queued Analog-to-Digital Converter (QADC)
3FF
3FE
nc...
Freescale Semiconductor, I
10-BIT RESULT (HEXADECIMAL)
3FD
3FC
3FB
3FA
18.11.3 Conversion Timing Schemes
8
7
6
5
4
3
2
1
0 .010 .020 .030 5.100 5.110 5.120 5.130
Figure 18-46. Errors Resulting from Clipping
This section contains some conversion timing examples. Figure 18-47
shows the timing for basic conversions where it is assumed that:
• Q1 begins with CCW0 and ends with CCW3.
• CCW0 has pause bit set.
INPUTS IN VOLTS (V RH = 5.120 V, V RL = 0 V)
• CCW1 does not have pause bit set.
• External trigger rise edge for Q1.
• CCW4 = BQ2 and Q2 is disabled.
• Q1 Res shows relative result register updates.
Recall that when QS = 0, both queues are disabled, when QS = 8,
queue 1 is active and queue 2 is idle, and when QS = 4, queue 1 is
paused and queue 2 is disabled.
Technical Data MMC2107 – Rev. 2.0
488 Queued Analog-to-Digital Converter (QADC) MOTOROLA
For More Information On This Product,
Go to: www.freescale.com