Fast Models Reference Manual - ARM Information Center

Processor Components
Table 4-41 ARM1136CT parameters (continued)
Parameter Description Type Values Default
semihosting-stack_limit
virtual address of stack
limit
integer 0x00000000 -
0xFFFFFFFF
0x0F0000000
vfp-enable_at_reset d
enable coprocessor access
and VFP at reset
boolean true/false false
vfp-present
configure processor as VFP boolean true/false true
enabled e
a. Specifying false models enables modeling a different number of TLBs if this improves simulation performance.
The simulation is architecturally accurate, but not device accurate. Architectural accuracy is almost always
sufficient. Specify true if device accuracy is required.
b. The value of argv[0] points to the first command line argument, not to the name of an image.
c. Currently ignored.
d. This is model specific behavior with no hardware equivalent.
e. This parameter lets you disable the VFP features of the model. However the model has not been validated as a
true ARM1136J-S processor.
4.14.4 Registers
The ARM1136CT component provides the registers specified by the technical reference manual
for the ARM1136JF-S with the following exceptions:
• coprocessor 14 registers are not implemented
• integration and test registers are not implemented.
4.14.5 Debug features
The ARM1136CT component exports a CADI debug interface.
Registers
All processor, VFP and CP15 registers, apart from performance counter registers, are visible in
the debugger. See the processor technical reference manual for a detailed description of
available registers.
The CP14 DSCR register is visible for compatibility reasons with some debuggers. This register
has no defined behavior.
Breakpoints
There is direct support for:
• single unconditional instruction breakpoints
• unconditional instruction range breakpoints
• single unconditional data breakpoints.
The debugger might augment these with more complex combinations of breakpoints.
The current models support processor exception breakpoints by the use of pseudo-registers
available in the debugger register window. When debugger support is added to directly support
processor exceptions, these pseudo-registers are removed.
Setting an exception register to a non-zero value causes execution to stop on entry to the
associated exception vector.
ARM DUI 0423J Copyright © 2008-2011 ARM. All rights reserved. 4-78
ID051811
Non-Confidential