Fast Models Reference Manual - ARM Information Center

Processor Components
Table 4-6 ARMCortexA9MPxnCT individual processor parameters a (continued)
Parameter Description Type
Allowed
value
Default
value
semihosting-debug d
semihosting-enable
Enable debug output of semihosting
SVC calls.
Enable semihosting SVC traps.
Caution
Applications that do not use
semihosting must set this parameter to
false.
boolean true/false false
boolean true/false true
semihosting-ARM_SVC ARM SVC number for semihosting. integer 0x000000 -
0xFFFFFF
0x123456
semihosting-Thumb_SVC Thumb SVC number for semihosting. integer 0x00 - 0xFF 0xAB
semihosting-heap_base Virtual address of heap base. integer 0x00000000 -
0xFFFFFFFF
semihosting-heap_limit Virtual address of top of heap. integer 0x00000000 -
0xFFFFFFFF
0x0
0x0F000000
semihosting-stack_base
Virtual address of base of descending
stack.
integer 0x00000000 -
0xFFFFFFFF
0x10000000
semihosting-stack_limit Virtual address of stack limit. integer 0x00000000 -
0xFFFFFFFF
0x0F000000
vfp-enable_at_reset e
Enable coprocessor access and VFP at
reset.
boolean true/false false
vfp-present b Set whether model has VFP support. boolean true/false true
a. For the ARMCortexA9MPxnCT processors, the instance name for each processor consists of the normal instance name (in
the provided examples, cortile.core) with a per-processor suffix. For example the first processor in the example
Cortex-A9MP platform has the instance name cortile.core.cpu0.
b. The ase-present and vfp-present parameters configure the synthesis options for the Cortex-A9 model. The options are:
vfp present and ase present
NEON and VFPv3-D32 supported.
vfp present and ase not present
VFPv3-D16 supported.
vfp not present and ase present
Illegal. Forces vfp-present to true so model has NEON and VFPv3-D32 support.
vfp not present and ase not present
Model has neither NEON nor VFPv3-D32 support.
c. The value of argv[0] points to the first command line argument, not to the name of an image.
d. Currently ignored.
e. This is a model specific behavior with no hardware equivalent.
4.3.4 Registers
The ARMCortexA9MPxnCT component provides the registers specified by the technical
reference manual for the Cortex-A9 processor with the following exceptions:
• coprocessor 14 registers are not implemented
• integration and test registers are not implemented.
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