Fast Models Reference Manual - ARM Information Center

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Peripheral and Interface Components Name Port protocol Type Description pvbus_distributor PVBus Slave Slave port for connection to distributor interface enable_c [8] Value Slave Compared with masked PVBus master id to select cpu interface: (master_id & enable_c) == match_c match_c [8] Value Slave Mask on the PVBus master id to select cpu interface: (master_id & enable_c) == match_c enable_d [8] Value Slave Compared with masked PVBus master id to select distributor interface: (master_id & enable_d) == match_d match_d [8] Value Slave Mask on the PVBus master id to select distributor interface: (master_id & enable_d) == match_d legacy_nfiq [8] Signal Slave Legacy FIQ interrupt for CPU Interface legacy_nirq [8] Signal Slave Legacy IRQ interrupt for CPU Interface cfgsdisable Signal Slave Set preventing write accesses to security-critical configuration registers reset_in Signal Slave Reset signal Table 5-79 PL390_GIC ports (continued) spi [988] Signal Slave Shared peripheral interrupt inputs Additional protocols The PL390_GIC component has no additional protocols. Parameters Table 5-80 provides a description of the configuration parameters for the PL390_GIC component. Table 5-80 PL390_GIC configuration parameters Parameter name Description Type Allowed value Default value ARCHITECTURE_VERSION Set architecture version in periph_id register Integer 0 - 1 1 AXI_IF Boolean true/false true C_ID_WIDTH Width of the cpu interface master id Integer 0 - 32 32 ARM DUI 0423J Copyright © 2008-2011 ARM. All rights reserved. 5-103 ID051811 Non-Confidential
Peripheral and Interface Components Table 5-80 PL390_GIC configuration parameters (continued) Parameter name Description Type Allowed value Default value D_ID_WIDTH ENABLE_LEGACY_FIQ ENABLE_LEGACY_FIQ Width of the distributor interface master id Provide legacy fiq interrupt inputs Provide legacy irq interrupt inputs Integer 0 - 32 32 Boolean true/false true Boolean true/false true ENABLE_PPI_EDGE ppi edge sensitive Boolean true/false false ENABLE_TRUSTZONE Support trust zone Boolean true/false true INIT_ENABLE_C0 to INIT_ENABLE_C7 INIT_ENABLE_D0 to INIT_ENABLE_D7 INIT_MATCH_C0 to INIT_MATCH_C7 INIT_MATCH_D0 to INIT_MATCH_D7 NUM_CPU NUM_LSPI NUM_PPI init value of ENABLE_C init value of ENABLE_D init value of MATCH_C init value of MATCH_D Number of cpu interfaces Number of lockable SPIs Number of private peripheral interrupts Integer - 0xFFFFFFFF Integer - 0xFFFFFFFF Integer - 0xFFFFFFFF Integer - 0xFFFFFFFF Integer 1 - 8 8 Integer 0 - 31 31 Integer 0 - 16 16 NUM_PRIORITY_LEVELS Number of priority levels Integer 16, 32, 64, 128, 256 256 NUM_SGI NUM_SPI Number of software generated interrupts Number of shared peripheral interrupts Integer 0 - 16 16 Integer 0 - 988 988 Registers Table 5-81 on page 5-105 and Table 5-82 on page 5-109 provide a description of the configuration registers for the PL390_GIC component. In these tables corresponds to the number of a CPU interface. A CPU interface consists of a pair of interfaces: pvbus_cpu and pvbus_distributor. The enable_c and match_c signals identify the originator of a transaction on pvbus_cpu. Similarly, enable_d and match_d signals are used to identify the originator of a transaction on pvbus_distributor. Note To reduce compile time, the registers are not available by default. To activate them uncomment one of the following statements in PL390_GIC.lisa: // #define FEW_CADI_REGISTER ARM DUI 0423J Copyright © 2008-2011 ARM. All rights reserved. 5-104 ID051811 Non-Confidential
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Fast Models Version 6.1 Reference M
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Contents Fast Models Reference Manu
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Preface This preface introduces the
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Preface Typographical conventions T
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Preface Feedback ARM welcomes feedb
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Introduction 1.1 About the componen
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Accuracy and Functionality 2.1 Mode
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Accuracy and Functionality 2.2.2 Pe
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Accuracy and Functionality 2. For a
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Accuracy and Functionality Fast Mod
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Signaling and Clocking Protocols 3.
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Signaling and Clocking Protocols 3.
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Signaling and Clocking Protocols Pa
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Signaling and Clocking Protocols Ve
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Chapter 4 Processor Components This
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Processor Components 4.2 ARMCortexA
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Processor Components InstructionCou
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Processor Components c. This is a m
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Processor Components Table 4-4 ARMC
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Processor Components 4.3.9 Library
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Processor Components a. The ase-pre
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Processor Components 4.4.8 Performa
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Processor Components 4.5.3 Paramete
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Processor Components The debugger m
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Processor Components 4.6.1 Ports Ta
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Processor Components Table 4-13 ARM
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Processor Components 4.6.5 Caches T
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Processor Components 4.7.8 Performa
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Processor Components Name Port Prot
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Processor Components b. Currently i
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Processor Components 4.9 ARMCortexR
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Processor Components 4.9.9 Library
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Processor Components Name Port prot
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Processor Components The debugger m
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Processor Components 4.11 ARMCortex
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Processor Components 4.12 ARMv7A -
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Processor Components pwrctli[0-3] V
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Processor Components Table 4-29 Pro
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Processor Components Cache geometry
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Processor Components Note In the vi
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Processor Components Message config
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Processor Components All entries in
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Processor Components 4.13.3 Paramet
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Processor Components Memory The ARM
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Processor Components Memory The ARM
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Processor Components 4.15.5 Debug f
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Processor Components 4.16 ARM926CT
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Processor Components Registers All
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Processor Components • Data/Instr
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Processor Components DMA DMA is cur
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Processor Components Table 4-47 Cor
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Peripheral and Interface Components
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Versatile Express Model: Platform a
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Chapter 7 Emulation Baseboard Model
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Emulation Baseboard Model: Platform
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Microcontroller Prototyping System:
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AEM ARMv7-A specifics A.1 Boundary
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AEM ARMv7-A specifics When paramete
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AEM ARMv7-A specifics When stepping
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AEM ARMv7-A specifics A.2 Debug arc
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AEM ARMv7-A specifics A.3 IMPLEMENT
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AEM ARMv7-A specifics A.4 Trace The
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Glossary DSR DTR EB GIC GPIO I/O KM
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