Fast Models Reference Manual - ARM Information Center

Accuracy and Functionality
Real processors attempt to prefetch instructions ahead of execution and predict branch
destinations to keep the prefetch queue full. The instruction prefetch behavior of a processor can
be observed by a program that writes into its own prefetch queue (without using explicit
barriers). The architecture does not define the results.
The CT engine processes code in blocks. The effect is as if the processor filled its prefetch queue
with a block of instructions, then executed the block to completion. As a result, this virtual
prefetch queue is sometimes larger and sometimes smaller than the corresponding hardware. In
the current implementation, the virtual prefetch queue can follow small forward branches.
With an L1 instruction cache turned on, the instruction block size is limited to a single
cache-line. The processor ensures that a line is present in the cache at the point where it starts
executing instructions from that line.
In real hardware, the effects of the instruction prefetch queue are to cause additional fetch
transactions, some of these are redundant because of incorrect branch prediction. This causes
extra cache and bus pressure.
2.3.4 Out-of-order execution and write-buffers
The current CT implementation always executes instructions sequentially in program order. One
instruction is completely retired before the next starts to execute. In a real processor, multiple
memory accesses can be outstanding at once, and can complete in a different order from their
program order. Writes can also be delayed in a write-buffer.
The programmer visible effects of these behaviors is defined in the architecture as the Weakly
Ordered memory model, which the programmer must be aware of when writing lock-free
multi-processor code.
Within Fast Models, all memory accesses can be observed to happen in program order,
effectively as if all memory is Strongly Ordered.
2.3.5 Caches
The effects of caches are programmer visible because they can cause a single memory location
to exist as multiple inconsistent copies. If caches are not correctly maintained, reads can observe
stale copies of locations, and flushes/cleans can cause writes to be lost.
There are three ways in which incorrect cache maintenance can be programmer visible:
From the D-Side interface of a single processor
The only way of detecting the presence of caches is to create aliases in the
memory map, so that the same range of physical addresses can be observed as
both cached and non-cached memory.
From the D-Side of a single processor to its I-Side
Stale instruction data can be fetched when new instructions have been written by
the D-side. This can either be due to deliberate self-modifying code, or as a
consequence of incorrect OS demand paging.
Between one processor and another device
For example, another processor in a non-coherent MP system, or an external
DMA device.
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