Fast Models Reference Manual - ARM Information Center

Versatile Express Model: Platform and Components
6.7.6 Timing considerations
The Real-Time System Models provide an environment that enables running software
applications in a functionally-accurate simulation. However, because of the relative balance of
fast simulation speed over timing accuracy, there are situations where the models might behave
unexpectedly.
When code interacts with real world devices like timers and keyboards, data arrives in the
modeled device in real-world (or wall-clock) time, but simulation time can be running much
faster than the wall clock. This means that a single keypress might be interpreted as several
repeated key presses, or a single mouse click incorrectly becomes a double click.
The VE RTSMs provide the Rate Limit feature to match simulation time to match wall-clock
time. Enabling Rate Limit, either by using the Rate Limit button in the CLCD display, or the
rate_limit-enable model instantiation parameter, forces the model to run at wall-clock time.
This avoids issues with two clocks running at significantly different rates. For interactive
applications, ARM recommends enabling Rate Limit.
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