Fast Models Reference Manual - ARM Information Center

AEM ARMv7-A specifics
A.1 Boundary features and architectural checkers
Boundary features and architectural checkers are model capabilities that help your development
and testing process by exposing latent problems in the target code. Certain boundary features or
architectural checkers, however, might have an adverse effect on the overall running speed of
target code. There are two reasons that this occurs:
• some checkers require the host CPU to perform extra work, for example to keep track of
historical information
• some features cause the simulated target processor to perform extra work, for example in
the number of steps required to perform cache maintenance.
As a result, you can optionally enable or disable checkers in cases where there is an impact on
performance. In the sections that follow, the effect of both the above factors on the total
execution time of a typical target operating system boot is indicated as a relative rating on a scale
from 1 to 5, where a larger number indicates a greater impact on speed.
A.1.1
Aggressively pre-fetching TLB
Rating: 2.
The architecture describes that a processor might at any time request the pagetable entry or
entries corresponding to any virtual address. When the boolean parameter vmsa.tlb_prefetch is
set as true, the AEM actively monitors the memory for all pagetables, and immediately updates
the Translation Lookaside Buffer (TLB) accounting for any changes.
Also, in this mode the TLB maintains state for old and new entries, and raises the message
E_StaleTLB if there is any possible ambiguity as to which entry could have been used in a
subsequent transaction.
Note
The aggressively pre-fetching TLB does not currently support the IMPLEMENTATION DEFINED TLB
lockdown feature described in TLB lockdown on page A-10. Lockdown registers are
non-operational when the pre-fetching TLB option is in use.
Note
The aggressively pre-fetching TLB does not currently support the Large Physical Address or
Virtualization features. TLB pre-fetching does not occur when either lpae or virtualization is
implemented in the processor.
A.1.2
Passive infinite TLB
Rating: 1.
You can safely set the parameters vmsa.main_tlb_size and vmsa.instruction_tlb_size to
arbitrarily large values. Entries are fetched only when they are used, but remain in the TLB until
no space remains or the entry is explicitly flushed out.
A.1.3
Infinite write buffer
Rating: 4.
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