Fast Models Reference Manual - ARM Information Center

Processor Components
4.6.9 Library dependencies
The ARMCortexA5MPxnCT component has no dependencies on external libraries.
4.6.10 Differences between the CT model and RTL implementations
The ARMCortexA5MPxnCT component differs from the corresponding revision of the ARM
Cortex-A5 RTL implementation in the following ways:
• There is a single memory port combining instruction, data, DMA and peripheral access.
• The ARMCortexA5MPxnCT does not implement address filtering within the SCU. The
enable bit for this feature is ignored.
• The GIC does not respect the CFGSDISABLE signal. This leads to some registers being
accessible when they must not be.
• The SCU enable bit is ignored. The SCU is always enabled.
• The SCU ignores the invalidate all register.
• The Broadcast TLB or cache operations in the ARMCortexA5MPxnCT model do not
cause other processors in the cluster which are asleep due to Wait For Interrupt(WFI) to
wake up.
• The RR bit in the SCTLR is ignored.
• The Power Control Register in the system control coprocessor is implemented but writing
to it does not change the behavior of the model.
• When modelling the SCU, coherency operations are represented by a memory write
followed by a read to refill from memory, rather than using cache-to-cache transfers.
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