Fast Models Reference Manual - ARM Information Center

Peripheral and Interface Components
The PL022_SSP component is a programmer's view model of the ARM PL022 Synchronous
Serial Port (SSP) PrimeCell. Although the PL022_SSP component has clock input, it is not
internally clock-driven. This is different to the equivalent hardware.
Refer to the component documentation for more details. See the ARM PrimeCell Synchronous
Serial Port (PL022) Technical Reference Manual.
Figure 5-24 shows a view of the component in System Canvas.
This component is written in LISA+.
Figure 5-24 PL022_SSP in System Canvas
Ports
Table 5-35 provides a brief description of the PL022_SSP ports. Refer to the component
documentation for more details.
Name Port protocol Type Description
Table 5-35 PL022_SSP ports
clk ClockSignal Slave Main PrimeCell SSP clock input.
clkin ClockSignal Slave PrimeCell SSP clock input.
pvbus PVBus Slave Slave port for connection to PV bus
master/decoder.
rxd ValueState Slave PrimeCell SSP receive data.
clkout ClockSignal Master Clock output.
intr Signal Master Interrupt signaling.
rorintr Signal Master Receive overrun interrupt.
rtintr Signal Master Receive timeout interrupt a .
rx_dma_port PL080_DMAC_DmaPortProtocol b Master PrimeCell SSP receive DMA port.
rxintr Signal Master Receive FIFO service request port.
tx_dma_port PL080_DMAC_DmaPortProtocol b Master PrimeCell SSP transmit DMA port.
txd ValueState Master PrimeCell SSP transmit data.
txintr Signal Master Transmit FIFO service request.
a. Not supported.
ARM DUI 0423J Copyright © 2008-2011 ARM. All rights reserved. 5-48
ID051811
Non-Confidential