Fast Models Reference Manual - ARM Information Center

Peripheral and Interface Components
Registers
Table 5-38 provides a description of the configuration registers for the PL030_RTC component.
See the PL030 documentation for further details.
Table 5-38 PL030_RTC registers
Register
name
Offset Access Description
RTCDR 0x00 read only Data register.
RTCMR 0x04 read/write Match register.
RTCSTAT 0x08 read only Interrupt status register.
RTCEOI 0x08 write only Interrupt clear register.
RTCLR 0x0C read/write Counter load register.
RTCCR 0x10 read/write Counter register.
Debug features
The PL030_RTC component has no debug features.
Verification and testing
The PL030_RTC component has been tested as part of the VE example system using VE test
suites and by booting operating systems.
Performance
The PL030_RTC component has no impact on the performance of a PV system when idle or
counting down. The component only executes code when the counter expires or during bus
accesses.
Library dependencies
The PL030_RTC component has no dependencies on external libraries.
5.4.7 PL031_RTC component
The PL031_RTC component is a programmer's view model of the PL031 Real Time Clock. It
can be used to provide a basic alarm function or long time base counter. For a detailed
description of the behavior of the PL031_RTC, read the component documentation. See the
ARM PrimeCell Real Time Clock (PL031) Technical Reference Manual.
Figure 5-26 shows a view of the component in System Canvas.
This component is written in LISA+.
Figure 5-26 PL031_RTC in System Canvas
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