Fast Models Reference Manual - ARM Information Center

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Peripheral and Interface Components • Lockdown format C supported, for data and instructions. Lockdown format C is also known as way locking. • Lockdown by line supported. • Lockdown by master id supported. • Direct mapped to 16-way associativity, depending on the configuration and the use of lockdown registers. The associativity is configurable as 8 or 16. • L2 cache available size can be 16KB to 8MB, depending on configuration and the use of the lockdown registers. • Fixed line length of 32 bytes (eight words or 256 bits). • Supports all of the AXI cache modes: — write-through and write-back. — read allocate, write allocate, read and write allocate. • Force write allocate option to always have cacheable writes allocated to L2 cache, for processors not supporting this mode. • Normal memory non-cacheable shared reads are treated as cacheable non-allocatable. Normal memory non-cacheable shared writes are treated as cacheable write-through no write-allocate. There is an option, Shared Override, to override this behavior. • TrustZone support, with the following features: — Non-Secure (NS) tag bit added in tag RAM and used for lookup in the same way as an address bit. — NS bit in Tag RAM used to determine security level of evictions to L3. — Restrictions for NS accesses for control, configuration, and maintenance registers to restrict access to secure data. • Pseudo-Random victim selection policy. You can make this deterministic with use of lockdown registers. • Software option to enable exclusive cache configuration. • Configuration registers accessible using address decoding in the component. • Interrupt triggering in case of an error response when accessing L3. • Maintenance operations. • Prefetching capability. Hardware features not implemented The following features of the PL310 hardware are not implemented in the PL310 model, most of them are not relevant from a PV modelling point of view: • There is no interface to the data and tag RAM as they are embedded to the model. • Critical word first linefill not supported, as this is not relevant for PV modelling. • Buffers are not modeled. • Outstanding accesses on slave and master ports cannot occur by design in a PV model as all transactions are atomic. ARM DUI 0423J Copyright © 2008-2011 ARM. All rights reserved. 5-91 ID051811 Non-Confidential
Peripheral and Interface Components • Option to select one or two master ports and option to select one or two slave ports is not supported. Only one master port and one slave port is supported. • Clock management and power modes are not supported, as they is not relevant for PV modelling. • Wait, latency, clock enable, parity, and error support for data and tag RAMs not included, as this is not relevant for PV modeling, and the data and tag RAMs embedded in the model cannot generate error responses. • MBIST support is not included. • Debug mode and debug registers are not supported. • Test mode and scan chains are not supported. • L2 cache event monitoring is not supported. • Address filtering in the master ports is not supported. • Performance counters are not supported. • Specific Cortex-A9 related optimizations are not supported: Prefetch hints, Full line of zero and Early write response. • Hazard detection is not required because of the atomic nature of the accesses at PV modelling and the fact that buffers are not modeled, thus hazards cannot occur. Registers belonging to features not implemented are accessible but do not have a functionality. Features additional to the Hardware • Data RAM and Tag RAM are embedded to the model. Features different to the Hardware • Error handling. DECERR from the master port is mapped to SLVERR. Internal errors in cache RAM (like parity errors) cannot happen in the model. • Background cache operations do not occur in the background. They occur atomically. • The LOCKDOWN_BY_LINE and LOCKDOWN_BY_MASTER parameter values are reflected in the CacheType register, but the feature is not switched off when the parameter is 0. 5.4.22 PL340_DMC component The PL340_DMC component is a programmer's view model of the ARM PL340 Dynamic Memory Controller (DMC). It provides an interface for up to four DRAM chips. The implementation also provides an apb_interface to configure the controller behavior. Further information is available in the component documentation. See the ARM PrimeCell Dynamic Memory Controller (PL340) Technical Reference Manual. Figure 5-42 on page 5-93 shows a view of the component in System Canvas. ARM DUI 0423J Copyright © 2008-2011 ARM. All rights reserved. 5-92 ID051811 Non-Confidential
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Fast Models Version 6.1 Reference M
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Contents Fast Models Reference Manu
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Preface This preface introduces the
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Preface Typographical conventions T
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Preface Feedback ARM welcomes feedb
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Introduction 1.1 About the componen
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Accuracy and Functionality 2.1 Mode
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Accuracy and Functionality 2.2.2 Pe
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Accuracy and Functionality 2. For a
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Accuracy and Functionality Fast Mod
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Signaling and Clocking Protocols 3.
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Signaling and Clocking Protocols 3.
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Signaling and Clocking Protocols Pa
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Signaling and Clocking Protocols Ve
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Chapter 4 Processor Components This
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Processor Components 4.2 ARMCortexA
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Processor Components InstructionCou
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Processor Components c. This is a m
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Processor Components Table 4-4 ARMC
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Processor Components 4.3.9 Library
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Processor Components a. The ase-pre
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Processor Components 4.4.8 Performa
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Processor Components 4.5.3 Paramete
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Processor Components The debugger m
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Processor Components 4.6.1 Ports Ta
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Processor Components Table 4-13 ARM
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Processor Components 4.6.5 Caches T
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Processor Components 4.7.8 Performa
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Processor Components Name Port Prot
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Processor Components b. Currently i
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Processor Components 4.9 ARMCortexR
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Processor Components 4.9.9 Library
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Processor Components Name Port prot
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Processor Components The debugger m
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Processor Components 4.11 ARMCortex
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Processor Components 4.12 ARMv7A -
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Processor Components pwrctli[0-3] V
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Processor Components Table 4-29 Pro
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Processor Components Cache geometry
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Processor Components Note In the vi
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Processor Components Message config
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Processor Components All entries in
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Processor Components 4.13.3 Paramet
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Processor Components Memory The ARM
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Processor Components Memory The ARM
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Processor Components 4.15.5 Debug f
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Processor Components 4.16 ARM926CT
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Processor Components Registers All
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Processor Components • Data/Instr
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Processor Components DMA DMA is cur
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Processor Components Table 4-47 Cor
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Peripheral and Interface Components
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Versatile Express Model: Platform a
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Chapter 7 Emulation Baseboard Model
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Emulation Baseboard Model: Platform
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Microcontroller Prototyping System:
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AEM ARMv7-A specifics A.1 Boundary
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AEM ARMv7-A specifics When paramete
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AEM ARMv7-A specifics When stepping
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AEM ARMv7-A specifics A.2 Debug arc
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AEM ARMv7-A specifics A.3 IMPLEMENT
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AEM ARMv7-A specifics A.4 Trace The
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Glossary DSR DTR EB GIC GPIO I/O KM
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