Fast Models Reference Manual - ARM Information Center

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Peripheral and Interface Components target_sgi_i0_0-3 0xDn800 read only ICDIPTR: SGI Target Register Interrupt ID 0-3 ... target_sgi_i0_12-15 0xDn80C read only ICDIPTR: SGI Target Register Interrupt ID 12-15 target_ppi_i0_0-3 0xDn810 read only ICDIPTR: PPI Target Register Interrupt ID 16-19 ... target_ppi_i0_12-15 0xDn81C read only ICDIPTR: PPI Target Register Interrupt ID 28-31 target_spi_0-3 0xD0820 read/write ICDIPTR: SPI Target Register Interrupt ID 32-35 ... target_spi_984-987 0xD0BF8 read/write ICDIPTR: SPI Target Register Interrupt ID 32-35 sgi_config_if_0-15 0xDnC00 read only ICDICR: SGI Interrupt Configuration Register Interrupt ID 0-15 ppi_config_if_0-15 0xDnC04 read only ICDICR: SGI Interrupt Configuration Register Interrupt ID 0-15 spi_config_0-15 0xD0C08 read/write ICDICR: SPI Interrupt Configuration Register Interrupt ID 32-47 ... spi_config_976-987 0xD0CFC read/write ICDICR: SPI Interrupt Configuration Register Interrupt ID 1008-1019 ppi_if 0xDnD00 read only ICDICR: SPI Interrupt Configuration Register Interrupt ID 1008-1019 spi_0-31 0xD0D04 read only ICDICR: SPI Interrupt Configuration Register Interrupt ID 1008-1019 ... Table 5-81 PL 390_GIC registers: Distributor Interface (continued) Register name Offset Access Description spi_960-987 0xD0D7C read only SPI Status Register Interrupt ID 992-1019 legacy_int 0xDnDD0 read only Legacy Interrupt Register match_d 0xDnDE0 read only Match Register enable_d 0xDnDE4 read only Enable Register ARM DUI 0423J Copyright © 2008-2011 ARM. All rights reserved. 5-107 ID051811 Non-Confidential
Peripheral and Interface Components Table 5-81 PL 390_GIC registers: Distributor Interface (continued) Register name Offset Access Description sgi_control 0xD0F00 read/write ICDSGIR: Software Generated Interrupt Register periph_id_d_8 0xD0FC0 read only Peripheral Identification Register 8 periph_id_d_4-7 0xD0FD0 read only Peripheral Identification Register [7:4] periph_id_d_0-3 0xD0FE0 read only Peripheral Identification Register [7:4] component_id 0xD0FF0 read only PrimeCell Identification Register Debug features The PL390_GIC component provides some registers for functional verification and integration testing. For detailed information refer to the Technical Reference Manual. Verification and testing The PL390_GIC has been run against the RTL validation suite and has been successfully used in validation platforms. Performance The PL390_GIC component is not expected to significantly affect the performance of a PV system. Library dependencies The PL390_GIC component has no dependencies on external libraries. 5.4.26 SP804_Timer component The SP804_Timer component is a programmer's view model of the ARM Dual-Timer module. For a detailed description of the behavior of the SP804 timer, refer to other documentation. See the ARM Dual-Timer Module (SP804) Technical Reference Manual. Figure 5-46 shows a view of the component in System Canvas. This component is written in LISA+. Figure 5-46 SP804_Timer in System Canvas ARM DUI 0423J Copyright © 2008-2011 ARM. All rights reserved. 5-108 ID051811 Non-Confidential
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Fast Models Version 6.1 Reference M
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Contents Fast Models Reference Manu
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Preface This preface introduces the
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Preface Typographical conventions T
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Preface Feedback ARM welcomes feedb
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Introduction 1.1 About the componen
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Accuracy and Functionality 2.1 Mode
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Accuracy and Functionality 2.2.2 Pe
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Accuracy and Functionality 2. For a
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Accuracy and Functionality Fast Mod
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Signaling and Clocking Protocols 3.
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Signaling and Clocking Protocols 3.
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Signaling and Clocking Protocols Pa
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Signaling and Clocking Protocols Ve
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Chapter 4 Processor Components This
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Processor Components 4.2 ARMCortexA
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Processor Components InstructionCou
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Processor Components c. This is a m
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Processor Components Table 4-4 ARMC
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Processor Components 4.3.9 Library
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Processor Components a. The ase-pre
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Processor Components 4.4.8 Performa
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Processor Components 4.5.3 Paramete
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Processor Components The debugger m
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Processor Components 4.6.1 Ports Ta
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Processor Components Table 4-13 ARM
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Processor Components 4.6.5 Caches T
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Processor Components 4.7.8 Performa
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Processor Components Name Port Prot
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Processor Components b. Currently i
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Processor Components 4.9 ARMCortexR
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Processor Components 4.9.9 Library
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Processor Components Name Port prot
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Processor Components The debugger m
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Processor Components 4.11 ARMCortex
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Processor Components 4.12 ARMv7A -
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Processor Components pwrctli[0-3] V
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Processor Components Table 4-29 Pro
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Processor Components Cache geometry
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Processor Components Note In the vi
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Processor Components Message config
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Processor Components All entries in
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Processor Components 4.13.3 Paramet
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Processor Components Memory The ARM
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Processor Components Memory The ARM
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Processor Components 4.15.5 Debug f
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Processor Components 4.16 ARM926CT
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Processor Components Registers All
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Processor Components • Data/Instr
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Processor Components DMA DMA is cur
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Processor Components Table 4-47 Cor
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Peripheral and Interface Components
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Versatile Express Model: Platform a
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Chapter 7 Emulation Baseboard Model
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Emulation Baseboard Model: Platform
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Microcontroller Prototyping System:
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AEM ARMv7-A specifics A.1 Boundary
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AEM ARMv7-A specifics When paramete
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AEM ARMv7-A specifics When stepping
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AEM ARMv7-A specifics A.2 Debug arc
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AEM ARMv7-A specifics A.3 IMPLEMENT
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AEM ARMv7-A specifics A.4 Trace The
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Glossary DSR DTR EB GIC GPIO I/O KM
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