Fast Models Reference Manual - ARM Information Center

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Peripheral and Interface Components Ports Table 5-84 provides a brief description of the SP805_Watchdog component ports. For more details, refer to the component documentation. See the ARM Watchdog Module (SP805) Technical Reference Manual. Name Port protocol Type Description Table 5-84 SP805_Watchdog ports pvbus_s PVBus Slave Slave port for connection to PV bus master/decoder irq_out Signal Master Interrupt signaling reset_out Signal Master Reset signaling clk_in ClockSignal Slave Clock input, typically 1MHz, driving master count rate reset_in Signal Master Master reset signal Additional protocols The SP805_Watchdog component has no additional protocols. Parameters Table 5-85 provides a description of the configuration parameter for the SP805_Watchdog component. Table 5-85 SP805_Watchdog configuration parameters Parameter name Description Type Allowed value Default value simhalt If true, Halt simulation instead of signalling reset Boolean true/false false Registers Table 5-86 provides a description of the configuration registers for the SP805_Watchdog component. Table 5-86 SP805_Watchdog registers Register name Offset Access Description SP805_WDOG_Load 0x000 read/write Load register SP805_WDOG_VALUE 0x004 read only Value register SP805_WDOG_CONTROL 0x008 read/write Control register SP805_WDOG_INT_CLR 0x00C write only Clear interrupt register ARM DUI 0423J Copyright © 2008-2011 ARM. All rights reserved. 5-111 ID051811 Non-Confidential
Peripheral and Interface Components Table 5-86 SP805_Watchdog registers (continued) Register name Offset Access Description SP805_WDOG_RAW_INT_STATUS 0x00C read only Raw interrupt status register SP805_WDOG_MASKED_INT_STATUS 0x010 read only Masked interrupt status register SP805_WDOG_LOCK 0xC00 read/write Register access lock register Debug features The SP805_Watchdog component has no debug features. Verification and testing The SP805_Watchdog component has been tested as part of an integrated platform. Performance The SP805_Watchdog component is not expected to significantly affect the performance of a PV system. Library dependencies The SP805_Watchdog component has no dependencies on external libraries. 5.4.28 SP810_SysCtrl component The SP810_SysCtrl component is a programmer's view model of the System Controller in the PrimeXsys ® subsystem. For a detailed description of the behavior of the SP810, refer to other documentation. See the PrimeXsys System Controller (SP810) Technical Reference Manual. Figure 5-48 shows a view of the component in System Canvas. This component is written in LISA+. Figure 5-48 SP810_SysCtrl in System Canvas ARM DUI 0423J Copyright © 2008-2011 ARM. All rights reserved. 5-112 ID051811 Non-Confidential
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Fast Models Version 6.1 Reference M
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Contents Fast Models Reference Manu
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Preface This preface introduces the
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Preface Typographical conventions T
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Preface Feedback ARM welcomes feedb
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Introduction 1.1 About the componen
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Accuracy and Functionality 2.1 Mode
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Accuracy and Functionality 2.2.2 Pe
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Accuracy and Functionality 2. For a
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Accuracy and Functionality Fast Mod
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Signaling and Clocking Protocols 3.
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Signaling and Clocking Protocols 3.
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Signaling and Clocking Protocols Pa
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Signaling and Clocking Protocols Ve
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Chapter 4 Processor Components This
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Processor Components 4.2 ARMCortexA
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Processor Components InstructionCou
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Processor Components c. This is a m
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Processor Components Table 4-4 ARMC
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Processor Components 4.3.9 Library
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Processor Components a. The ase-pre
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Processor Components 4.4.8 Performa
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Processor Components 4.6.1 Ports Ta
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Processor Components Table 4-13 ARM
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Processor Components 4.9.9 Library
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Processor Components Cache geometry
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Processor Components Note In the vi
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Processor Components Message config
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Processor Components All entries in
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Processor Components 4.13.3 Paramet
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Processor Components Memory The ARM
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Processor Components Memory The ARM
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Processor Components 4.15.5 Debug f
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Processor Components 4.16 ARM926CT
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Processor Components Registers All
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Processor Components • Data/Instr
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Peripheral and Interface Components
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Chapter 7 Emulation Baseboard Model
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Emulation Baseboard Model: Platform
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Microcontroller Prototyping System:
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AEM ARMv7-A specifics A.1 Boundary
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AEM ARMv7-A specifics When paramete
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AEM ARMv7-A specifics When stepping
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AEM ARMv7-A specifics A.2 Debug arc
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AEM ARMv7-A specifics A.3 IMPLEMENT
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Glossary DSR DTR EB GIC GPIO I/O KM
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