Fast Models Reference Manual - ARM Information Center

Processor Components
4.8.9 Library dependencies
The ARMCortexR5CT component has no dependencies on external libraries.
4.8.10 Differences between the CT model and RTL Implementations
The ARMCortexR5CT component differs from the corresponding revision of the ARM
Cortex-R5 RTL implementation in the following ways:
• The RR bit in the SCTLR is ignored.
• The Low Latency Peripheral Port is not modeled.
• The model only has a single bus master port combining instruction, data, DMA and
peripheral accesses. The CP15 control registers associated with Peripheral buses preserve
values but do not have any other effect.
• The model only supports static split lock and not dynamic split lock. Contact ARM for
details.
• TCMs are modeled internally and the model does not support external TCMs or the ports
associated with them.
• The model cannot experience an ECC error and does not support fault injection into the
system, so we do not provide the ability to set error schemes for the caches or TCMs. If
you require a particular value in the Build Options registers despite this limitation, please
contact ARM.
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